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tecture to implement the traffic enforcer (or a traffic shaper at the customer premises as shown in Fig. 1) has been proposed in [151. This architecture is capable of performing the traffic enforcement for a large number of virtual channels (e.g., a few thousand) on each input line.

H. Jonathan Chao and Necdet UzunBellcore and Polytechnic University? is required to effectively and fairly allocate the shared The asynchronous transfer mode (ATM) technique provides a standardized and flexible scheme to transport and switch traffic effectively for different services. To provide satisfactory quality of service (QOS) to all users on the network, it is necessary to control the users' traffic so that network resources, such as transmission bandwidth and buffer capacity, can be efficiently and fairly utilized by all the users while still meeting the individual QOS requirement. However, due to the natural randomness of the broadband traffic (e.g., data file transfer and variable bit-rate video communication), it is difficult to control users' traffic effectively so that network congestion is prevented or, at least, occurs rarely. In this paper, we propose to control users' traffic at two places in the network: at the user-network interface (UNI) by a traffic enforcer, and at the network-node interface ("1) by a queue manager. The traffic enforcer adopted in our work contains a buffer to delay and reshape the violating cells that do not comply with some agreed-upon traffic parameters, and thus is also called a traffic shaper. The queue manager manages the queued cells in network nodes in such a way that higher priority cells are always served first, low priority cells are discarded when the queue is full, and any interference between same-priority cells is prevented. We present in the paper our proposed architectures for the traffic shaper and the queue manager. We have implemented and tested a key component, called the Sequencer chip, to realize both architectures. The Sequencer chip is implemented using 1 . 2 -~m CMOS technology. It contains about 150k transistors, has a die size of 7.5 mm x 8.3 mm, and is packaged in a 223-pin ceramic pin grid array P G A ) carrier.

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