A VLSI design of an arrayed pipelined Tomlinson-Harashima precoder for MU-MIMO systems

Shimazaki, Kosuke; Yoshizawa, Shingo; Hatakawa, Yasuyuki; Matsumoto, Tomoko; Konishi, Satoshi; Miyanaga, Yoshikazu

doi:10.1109/apsipa.2013.6694149

Cited by 4 publications

(5 citation statements)

References 8 publications

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“…The proposed ASIP performs very well in terms of throughput compared to [4] and [5]. In addition, the proposed ASIP is more realistic as it considers scheduling unlike the other implementations.…”

Section: Resultsmentioning

confidence: 92%

“…A DPC precoder based on nested trellis is implemented on FPGA in [4]. A Tomlinson-Harashima (TH) precoder is designed in [5] where the LQ decomposition is implemented in ASIP and the other parts are implemented as monolithic hardware.…”

Section: Resultsmentioning

confidence: 99%

“…Several hardware implementations for MU-MIMO precoding are proposed in [3], [4] and [5]. The fixed hardware implementations provide high data rate and consume less silicon area compared to the customized application specific processors (ASIP).…”

Section: Introductionmentioning

confidence: 99%

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ASIP design for multiuser MIMO broadcast precoding

Shahabuddin

Silvén

Juntti

2017

2017 European Conference on Networks and Communications (EuCNC)

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This paper presents an application-specific instruction-set processor (ASIP) for multiuser multiple-input multiple-output (MU-MIMO) broadcast precoding. The ASIP is designed for a base station (BS) with four antennas to perform user scheduling and precoding. Transport triggered architecture (TTA) is used as the processor template and high level language is used to program the ASIP. Several special function units (SFU) are designed to accelerate norm-based greedy user scheduling and minimum-mean square error (MMSE) precoding. We also program zero forcing dirty paper coding (ZF-DPC) to demonstrate the reusability of the ASIP. A single core provides a throughput of 52.17 Mbps for MMSE precoding and takes an area of 87.53 kgates at 200 MHz on 90 nm technology.

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Section: Resultsmentioning

confidence: 92%

Section: Resultsmentioning

confidence: 99%

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ASIP design for multiuser MIMO broadcast precoding

Shahabuddin

Silvén

Juntti

2017

2017 European Conference on Networks and Communications (EuCNC)

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“…A DPC precoder based on nested trellis is implemented on FPGA in [28]. A Tomlinson-Harashima (TH) precoder is designed in [29] where the LQ decomposition is implemented in ASIP and the other parts are implemented as monolithic hardware. A fixed sphere encoder (FSE) based precoder is presented in [30].…”

Section: Resultsmentioning

confidence: 99%

“…The performance of the precoders are listed in Table V. The proposed ASIP provides higher throughput than the FPGA implementation presented in [29]. The FPGA implementation of [30] provides significantly higher throughput.…”

Section: Resultsmentioning

confidence: 99%

Programmable ASIPs for Multimode MIMO Transceiver

Shahabuddin

Silvén

Juntti

2018

J Sign Process Syst

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Application specific instruction-set processors (ASIP) are a programmable and flexible alternative of traditional finite state machine (FSM) controlled registertransfer level (RTL) designs for multimode basedband systems. In this paper, we present two ASIPs for small scale multipleinput multiple-output (MIMO) wireless communication systems that demonstrate the soundness and effectiveness of ASIPs for this type of applications. The first ASIP is programmed with multiple MIMO symbol detection algorithms for 4 × 4 systems. The supported detection algorithms are minimum mean-square error (MMSE), two variants of the selective spanning with fast enumeration (SSFE) and K-best list sphere detection (LSD). The second ASIP supports MMSE and zero-forcing dirty paper coding (ZF-DPC) algorithms for a base station (BS) with 4 antennas and for 4 users. Both ASIPs are based on transport triggered architecture (TTA) and are programmed with a retargetable compiler with high level language to meet the time-to-market requirements. The detection and precoding algorithms can be switched in the respective ASIPs based on the error-rate requirements. Depending on the algorithms, MIMO detection ASIP delivers 6.16-66.66 Mbps throughput at a clock frequency of 200 MHz on 90 nm technology. The precoder ASIP provides a throughput of 52.17 and 51.95 Mbps for MMSE and ZF-DPC precoding respectively at a clock frequency of 210 MHz on 90 nm technology.

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