A VLSI architecture for advanced video coding motion estimation

Yap, Swee Yeow; McCanny, J.V.

doi:10.1109/asap.2003.1212853

Cited by 32 publications

(16 citation statements)

References 7 publications

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“…From Table I, the proposed architecture has the smallest on-chip memory size. It has higher gate count than the architecture in [2]- [4] however, it has higher throughput. The architecture in [5] has better throughput than the proposed architecture at the cost of larger gate count and on-chip memory size.…”

Section: Prototyping Resultsmentioning

confidence: 89%

“…The reported gate count is the estimated gate count by the synthesis tool "Synplify Pro." Table I compares between the proposed architecture and the architectures published in [2]- [5]. From Table I, the proposed architecture has the smallest on-chip memory size.…”

Section: Prototyping Resultsmentioning

confidence: 94%

“…Few of these architectures support variable block size motion estimation such as the ones presented in [2]- [6]. The architecture in [2] has 1-D PE array and uses a shuffling mechanism within each PE to combine the sum of absolute differences (SAD) values of smaller sub-blocks to find the SAD values of the larger blocks. The architecture in [3] is a reconfigurable architecture, which supports different search strategies.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Towards an H.264/AVC HW/SW Integrated Solution: An Efficient VBSME Architecture

Sayed

Badawy

Jullien

2008

IEEE Trans. Circuits Syst. II

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This paper presents an efficient real-time variable block size motion estimation architecture. The proposed architecture provides motion vectors for each 16 16 block and its 40 sub-blocks. The proposed architecture is a single-instruction multiple-data architecture integrated with embedded SRAMs on one chip. The architecture has been prototyped using Xilinx Virtex-4 XC4VSX35-10 field-programmable gate array. It processes 30-CIF fps using 71-MHz clock frequency. Its maximum clock frequency is 187.7 MHz and the maximum throughput is 20 4CIF fps. The prototyped architecture has 175 k gates and 18 kbits embedded SRAM.Index Terms-H.264, single-instruction multiple-data (SIMD) architecture, variable block size motion estimation (VBSME).

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Section: Prototyping Resultsmentioning

confidence: 89%

Section: Prototyping Resultsmentioning

confidence: 94%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Towards an H.264/AVC HW/SW Integrated Solution: An Efficient VBSME Architecture

Sayed

Badawy

Jullien

2008

IEEE Trans. Circuits Syst. II

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“…With 0.35 μm technology and a clock frequency of 67 MHz (the operating voltage is not stated) the design has a simulated power consumption of 737 mW without frame memories. In [19], a QCIF@15 fps implementation using variable block-size Full Search is presented. With 0.13 μm technology, a clock frequency of 6.7 MHz, and an operating voltage of 1.2 V the design has a simulated power consumption of 9.1 mW without frame memories.…”

Section: Related Workmentioning

confidence: 99%

An Analog Processor Array Implementing Interconnect-Efficient Reference Data Shift and SAD/SSD Extraction for Motion Estimation

Poikonen

Laiho

Paasio

et al. 2009

EURASIP J. Adv. Signal Process.

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A cellular analog processor array for use in variable block-size motion estimation with a new simple method for shifting reference image data is presented. The new shift method leads to a greatly reduced number of neighborhood connections for each cell of the array, and allows for all shifts within the [8,8] search area to be performed in a single step, with simple digital controls. The new shift circuitry, together with some other cell and system level optimizations , reduces silicon area and array layout complexity, enabling faster and more efficient parallel full search motion estimation hardware. A 32 × 32 cell parallel analog test array for reference-shift with a maximum block-size of 16 × 16, as well as absolute value/quadratic processing for variable block-size analog motion estimation (AME) has been designed in a 0.13 μm CMOS technology.

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“…Although VBS-BMA achieves higher coding performance than that of FBS-BMA, it requires a high computation effort since 41 motion vectors of 7 different sizes should be computed for each macroblock. Therefore, many efficient hardware architectures such as systolic array [8], 1-D processing element (PE) array [6] and 2-D PE array [4] [7] [10] have been proposed for implementing VBS-BMA. The 1-D PE array is a simple structure, as it is easier to control and less gates than a 2-D PE array, but it is normal to search the sum of absolute difference (SAD) against only one row or a column of the macroblock at a time.…”

Section: Introductionmentioning

confidence: 99%

An Efficient Hardware Architecture for Full-Search Variable Block Size Motion Estimation in H.264/AVC

Pyen

Min

Chong

et al. 2006

Advances in Visual Computing

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Abstract. In this paper, we propose a high speed hardware architecture for the implementation of full-search variable block size motion estimation (VBSME) suitable for high quality video compression. In the high-quality video with large frame size and search range, the memory bandwidth is mainly responsible for throughput limitations and power consumption in VBSME. The proposed architecture is designed for reducing the memory bandwidth by adopting "meander"-like scan for a high overlapped data of the search area and using onchip memory to reuse the overlapped data. We can reuse the previous candidate block of 94% to the current one and save about 23% memory access cycles in a search range of [-16, +15]. The architecture has been prototyped in Verilog HDL, simulated by ModelSim and synthesized by Synopsys Design Compiler with Samsung 0.18um standard cell library. Under a clock frequency of 51MHz, The simulation result shows that the architecture can achieve the realtime processing of 720x576 picture size at 30fps with the search range of [-16~+15].

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A VLSI architecture for advanced video coding motion estimation

Abstract: With the advent of new video standards such as

Cited by 32 publications

References 7 publications

Towards an H.264/AVC HW/SW Integrated Solution: An Efficient VBSME Architecture

Towards an H.264/AVC HW/SW Integrated Solution: An Efficient VBSME Architecture

An Analog Processor Array Implementing Interconnect-Efficient Reference Data Shift and SAD/SSD Extraction for Motion Estimation

An Efficient Hardware Architecture for Full-Search Variable Block Size Motion Estimation in H.264/AVC

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