An Efficient Hardware Architecture for Full-Search Variable Block Size Motion Estimation in H.264/AVC

Abstract

Abstract. In this paper, we propose a high speed hardware architecture for the implementation of full-search variable block size motion estimation (VBSME) suitable for high quality video compression. In the high-quality video with large frame size and search range, the memory bandwidth is mainly responsible for throughput limitations and power consumption in VBSME. The proposed architecture is designed for reducing the memory bandwidth by adopting "meander"-like scan for a high overlapped data of the search area and using onchip memory to reuse the overlapped data. We can reuse the previous candidate block of 94% to the current one and save about 23% memory access cycles in a search range of [-16, +15]. The architecture has been prototyped in Verilog HDL, simulated by ModelSim and synthesized by Synopsys Design Compiler with Samsung 0.18um standard cell library. Under a clock frequency of 51MHz, The simulation result shows that the architecture can achieve the realtime processing of 720x576 picture size at 30fps with the search range of [-16~+15].

An efficient hardware architecture for inter-prediction in H.264/AVC encoders

“…The designs presented in [3], [7]- [9] use full search as block-matching algorithm which is easy to be implemented in hardware and it has the best accuracy. However, the full search algorithm is not suitable for larger search ranges and very expensive in hardware implementation and computation power.…”