A video-rate JPEG chip set

Ruetz, P.A.; Tong, Po; Luthi, D.A.; Ang, Peng Hwa

doi:10.1007/bf01581291

Cited by 19 publications

(1 citation statement)

References 3 publications

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“…In similar, the clock rate achieved by JPEG architecture proposed in Hunter et al, Okada et al, Asada et al, Ruetz et al, and Sundari and Anita 16,17,19,11,18 is 30, 18, 30, 17.5, and 63 MHz, respectively, whereas in this work, the proposed system achieves higher rate of 36 MHz. In addition, the power consumed by various architectures is 840, 400, 500, 417, and 116.3 MW, respectively, as shown in Table 2.…”

Section: Resultssupporting

confidence: 54%

An efficient implementation of low‐power approximate compressor–based multiplier for cognitive communication systems

Sundhari¹

2019

Int J Communication

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Image compression is significant for resourceful transmission and storage of images. The multimedia data like image, audio, and videos are uploaded in the Internet through telecommunication networks. Actual image size plays when page utilization is higher. So image compression standard joint photographic experts group (JPEG) is used for storing images in a compressed format. The quality of JPEG is that it yields little loss in quality using high compression ratios. Multiplier and adder play a major hardware resource in JPEG compression. To reduce this, hardware complexity here proposed a compressor-based multiplier to increase the performance of JPEG standard as well as reducing the logic resources. This architecture is going to be implemented in CYCLONE IV FPGA with 512 × 512 and 640 × 480 resolutions of images.

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