A concurrent memory-efficient VLC decoder for MPEG applications

Hsieh, None Cheng-Teh; Kim, Seung P. Kim Seung P.

doi:10.1109/30.536141

IEEE Trans. Consumer Electron.

1996

DOI: 10.1109/30.536141

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A concurrent memory-efficient VLC decoder for MPEG applications

None Cheng-Teh Hsieh¹,

Seung P. Kim Seung P. Kim²

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Cited by 17 publications

References 7 publications

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A Cost-effective VLD Architecture for MPEG-2 and AVS

Mei

2007

J Sign Process Syst Sign Image Video Technol

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In this paper, we propose a cost-effective architecture of variable length decoder (VLD) for MPEG-2 and AVS. In order to save the buffer memory between VLD and IDCT and accelerate decoding speed, block-based pipeline buffers are adopted. Inverse scan (IScan) and inverse quantisation (IQ) are also merged into this architecture for cost-effective implementation and for easier system integration. A novel group-based architecture with the optimized look-up table is used for MPEG-2 and a new memory-efficient architecture with mixed memory organization is used for AVS. We use shared modules in both MPEG-2 and AVS as much as possible, such as the flush unit, the buffer controller and the buffers. Moreover, we propose merged IQ scheme and merged RAMs scheme. Based on 0.18 mm CMOS technology, the proposed design consumes about 11.5 K gates at a clock constrain of 125 MHz. The simulation results show that it can achieve real-time decoding, such as HD1080i (1,920Â1,088 at 30 MHz) format video of AVS and MPEG-2. Furthermore, we propose an effective design of the buffers between VLD and IDCT according to the IDCT architecture, a cost-efficient IQ architecture with full flexibility and an efficient scheme for accelerating VLC decoding.

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A Cost-effective VLD Architecture for MPEG-2 and AVS

Mei

2007

J Sign Process Syst Sign Image Video Technol

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A Novel Cost-Effective and Programmable VLSI Architecture of CAVLC Decoder for H.264/AVC

Mei

2007

J Sign Process Syst Sign Image

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This paper proposes a novel cost-effective and programmable architecture of CAVLC decoder for H.264/AVC, including decoders for Coeff_token, T1_sign, Level, Total_zeros and Run_before. To simplify the hardware architecture and provide programmability, we propose four new techniques: a new group-based VLD with efficient memory (NG-VLDEM) for Coeff_token decoder, a novel combined architecture (NCA) for level decoder, a new group-based VLD with memory access once (GMAO) for Total_zeros decoder and a new VLD architecture based on multiplexers instead of searching memory (MISM) for Run_before decoder. With the above four techniques, the proposed CAVLC decoder can decode every syntax element within one clock cycle. Synthesis result shows that the hardware cost is 3,310 gates with 0.18 mm CMOS technology at a clock constrain of 125 MHz. Therefore, the proposed design is satisfied for real-time applications, such as H.264/AVC HD1080i video decoding.

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A Low-Latency Multi-layer Prefix Grouping Technique for Parallel Huffman Decoding of Multimedia Standards

Tsai

Liu

2008

J Sign Process Syst Sign Image Video Technol

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Huffman coding is a popular and important lossless compression scheme for various multimedia applications. This paper presents a low-latency parallel Huffman decoding technique with efficient memory usage for multimedia standards. First, the multi-layer prefix grouping technique is proposed for sub-group partition. It exploits the prefix characteristic in Huffman codewords to solve the problem of table size explosion. Second, a two-level table lookup approach is introduced which can promptly branch to the correct subgroup by level-1 table lookup and decode the symbols by level-2 table lookup. Third, two optimization approaches are developed; one is to reduce the branch cycles and the other is parallel processing between two-level table lookup and direct table lookup approaches to fully utilize the advantage of VLIW parallel processing. An AAC Huffman decoding example is realized on the Parallel Architecture Core DSP (PAC DSP) processor. The simulation results show that the proposed method can further improve about 89% of decoding cycles and 33% of table size comparing to the linear search method.

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A concurrent memory-efficient VLC decoder for MPEG applications

Cited by 17 publications

References 7 publications

A Cost-effective VLD Architecture for MPEG-2 and AVS

A Cost-effective VLD Architecture for MPEG-2 and AVS

A Novel Cost-Effective and Programmable VLSI Architecture of CAVLC Decoder for H.264/AVC

A Low-Latency Multi-layer Prefix Grouping Technique for Parallel Huffman Decoding of Multimedia Standards

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