This paper proposes a novel cost-effective and programmable architecture of CAVLC decoder for H.264/AVC, including decoders for Coeff_token, T1_sign, Level, Total_zeros and Run_before. To simplify the hardware architecture and provide programmability, we propose four new techniques: a new group-based VLD with efficient memory (NG-VLDEM) for Coeff_token decoder, a novel combined architecture (NCA) for level decoder, a new group-based VLD with memory access once (GMAO) for Total_zeros decoder and a new VLD architecture based on multiplexers instead of searching memory (MISM) for Run_before decoder. With the above four techniques, the proposed CAVLC decoder can decode every syntax element within one clock cycle. Synthesis result shows that the hardware cost is 3,310 gates with 0.18 mm CMOS technology at a clock constrain of 125 MHz. Therefore, the proposed design is satisfied for real-time applications, such as H.264/AVC HD1080i video decoding.
As a iiew technique, MBAFF is added to H.264/AVC to achieve luglier compression efficiency for interlaced video nintaials. However, at the saiiie time ti12 coniplexity increases largely because of tlie triple-pass nature. of Uie algonUmi. Ilicrefore: redivxg the coding complexity by detectmg the encodiiig iiiocle of each MB is necessary. A novel fast MBAIF mod2 prediction strategy is proposed in this paper, it gives out a proinising estimation of the encoding mode for each MB and it requires only one pass of the data. Eqxriinent results prove that the proposed algoritlmi significantly reduces tlie coiilyutation of coduig; nhile preserving video quality to an acceptable level.
In this paper, a cost-effective architecture of variable length decoder (VLD) for MPEG-2 and AVS (Advanced Audio Video Coding Standard established in China, Part two, Ji Zhun Profile) is proposed. Inverse scan (IScan) and inverse quantisation (IQ) are also merged into this design for costeffective implementation. A novel group-based architecture with efficient symbol generation scheme is presented for MPEG-2 and a new memory-efficient architecture with mixed memory organization is presented for AVS. Furthermore, we analyze the algorithms of the two standards and propose a merged IQ scheme and a merged RAMs scheme. The proposed design consumes about 13.5K gates at a clock constrain of 166 MHz with 0.18ptm CMOS technology. The simulation results show that it can achieve real-time decoding, such as HD1O80i (1920x1088@30 MHz) format video of AVS and MPEG-2.
In this paper, we propose a cost-effective architecture of variable length decoder (VLD) for MPEG-2 and AVS. In order to save the buffer memory between VLD and IDCT and accelerate decoding speed, block-based pipeline buffers are adopted. Inverse scan (IScan) and inverse quantisation (IQ) are also merged into this architecture for cost-effective implementation and for easier system integration. A novel group-based architecture with the optimized look-up table is used for MPEG-2 and a new memory-efficient architecture with mixed memory organization is used for AVS. We use shared modules in both MPEG-2 and AVS as much as possible, such as the flush unit, the buffer controller and the buffers. Moreover, we propose merged IQ scheme and merged RAMs scheme. Based on 0.18 mm CMOS technology, the proposed design consumes about 11.5 K gates at a clock constrain of 125 MHz. The simulation results show that it can achieve real-time decoding, such as HD1080i (1,920Â1,088 at 30 MHz) format video of AVS and MPEG-2. Furthermore, we propose an effective design of the buffers between VLD and IDCT according to the IDCT architecture, a cost-efficient IQ architecture with full flexibility and an efficient scheme for accelerating VLC decoding.
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