A video DSP with a macroblock-level-pipeline and a SIMD type vector-pipeline architecture for MPEG2 codec

Toyokura, M.; Saishi, M.; Kurohmaru, S.; Yamauchi, K.; Imanishi, H.; Ougi, T.; Watabe, A.; Matsumoto, Y.; Morishige, T.; Kodama, H.; Miyagoshi, E.; Okamoto, K.; Gion, M.; Minemaru, T.; Ohtani, A.; Araki, T.; Aono, K.; Takeno, H.; Akiyama, T.; Wilson, B.

doi:10.1109/isscc.1994.344733

Cited by 19 publications

(5 citation statements)

References 4 publications

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“…MB) levels. Instead of purely MB-level [1] [3] and block-level [2] pipeline scheme, we make use of 4x4 sub-block-level pipeline architecture since a 4x4 sub-block is the smallest coding unit that H.264/AVC adopts. Additionally, due to a native algorithm of pixel dependency, a 16x16 MB-level pipelining is adopted to coordinate the data flow prior to de-blocking filter.…”

Section: A 4x4 Sub-block Level Pipeliningmentioning

confidence: 99%

An 865-μW H.264/AVC Video Decoder for Mobile Applications

Liu

Lin

Wang

et al. 2005

2005 IEEE Asian Solid-State Circuits Conference

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A low power H.264/AVC video decoder LSI for mobile applications is presented. Video decoding of quartercommon intermediate format (QCIF) sequence at 30 frames per second is achieved at 1.2MHz clock frequency and requires about 865µW at 1.8-V supply voltage. Moreover, CIF, SD and HD sequence format are also supported. The decoder architecture is based on 4x4 sub-block level pipelining that achieves better buffer allocation and decoding throughput. In addition, several modules are designed with new features to improve overall system throughput (up to 260,000 MacroBlock/sec). The proposed solution integrates 456-k logic gates with 161Kb of embedded SRAM in 0.18-µm single-poly sixmetal CMOS process with area of 11.3mm 2 .

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Section: A 4x4 Sub-block Level Pipeliningmentioning

confidence: 99%

An 865-μW H.264/AVC Video Decoder for Mobile Applications

Liu

Lin

Wang

et al. 2005

2005 IEEE Asian Solid-State Circuits Conference

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“…3) Coprocessor Approach: The VDSP2 [8] processing capabilities from Matsushita Electric are based on the use of an internal SIMD architecture of four DSP processors controlled by a DSP-core controller. In addition to this SIMD array, the circuit has special units for DCT and VLC.…”

Section: B Video Signal Processorsmentioning

confidence: 99%

“…The three main parts are the motion estimation, the coding loop, and the bitstream encoding. The motion estimation and coding loop manipulate 8 8, 16 8, or 16 16 pixel blocks and are well suited to data parallelism. Since the computation is very similar for each block, the use of an SIMD parallelism remains highly efficient.…”

Section: A Mpeg-2 Encoder Implementationmentioning

confidence: 99%

“…They are usually designed to be well suited to a specific application: volume and speed constraints are usually of major importance. Let us cite, for instance, the VDSP2 [8] from Matsushita Electric, which was designed for MPEG-1 and MPEG-2 (main profile at main level) encoding and decoding applications. Real-time MPEG-2 encoding requires two VDSP2 IC's and an external motion estimator.…”

Section: B Comparison With Other Vsp Approachesmentioning

confidence: 99%

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Toward hardware building blocks for software-only real-time video processing: the MOVIE approach

Charot

Fol

Lemonnier

et al. 1999

IEEE Trans. Circuits Syst. Video Technol.

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The goal of the movie very large-scale integration chip is to facilitate the development of software-only solutions for real-time video processing applications. This chip can be seen as a building block for single-instruction, multiple-data processing, and its architecture has been designed so as to facilitate high-level language programming. The basic architecture building block associates a subarray of computation processors with an I/O processor. A module can be seen as a small linear, systolic-like array of processing elements, connected at each end to the I/O processor. The module can communicate with its two nearest neighbors via two communication ports. The chip architecture also includes three 16-bit video ports. One important aspect in the programming environment is the C-stolic programming language. C-stolic is a C-like language augmented with parallel constructs, which allow the differentiation between the array controller variables (scalar variables) and the local variables in the array structure (systolic variables). A statement operating on systolic variables implies a simultaneous execution on all the cells of the structure. Implementation examples of movie-based architectures dealing with video compression algorithms are given.Index Terms-Code generation, single-instruction, multipledata (SIMD) architecture, systolic architecture, very large-scale integration (VLSI) circuit, video compression, video processing.

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“…Some of them studied the implementation [2][3] , but the problems caused by the increased FIFOs and buffers are often ignored. In this paper, we suggested a switching buffer module to substitute for the traditional FIFOs and buffers.…”

Section: Introductionmentioning

confidence: 99%

An improved asynchronous pipeline architecture for real-time video decoder implementation

2009

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Asynchronous pipeline structure is adopted for the real-time video decoder design because of its better performance when the stage processing times are irregular. However, the structure requires a lot of memories, the invaluable resource on chip, to buffer data and parameters between modules. To solve this problem, a specially designed switching buffer module is used between stages instead of traditional FIFO, and the module can also take some buffering function in each stage, which helps to reduce the utilization of memory. An H.264 decoder with the proposed structure was implemented. Compared to decoder without improved structure, the experimental decoder can save nearly 50% memory and 31% I/O operations between stages.

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A video DSP with a macroblock-level-pipeline and a SIMD type vector-pipeline architecture for MPEG2 codec

Cited by 19 publications

References 4 publications

An 865-μW H.264/AVC Video Decoder for Mobile Applications

An 865-μW H.264/AVC Video Decoder for Mobile Applications

Toward hardware building blocks for software-only real-time video processing: the MOVIE approach

An improved asynchronous pipeline architecture for real-time video decoder implementation

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