An 865-μW H.264/AVC Video Decoder for Mobile Applications

Liu, Tsu-Ming; Lin, Tsung-Nan; Wang, Sheng-Zen; Lee, Wen-Ping; Hou, Kang-Cheng; Yang, Jiun-Yan; Lee, Chen‐Yi

doi:10.1109/asscc.2005.251725

Cited by 17 publications

(17 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…They mainly include registers, SRAM, DRAM and disk hardware blocks for instruction and data storage. Meanwhile, many H.264/AVC video processors [5][6][7][8][9][10], have been reported of the time and adopt three-level memory hierarchy to keep the pixel data in registers, SRAM and frame DRAM. As the disparity between registers and DRAM, SRAM hierarchy design plays an increasing role in memory performance [3].…”

Section: Memory Hierarchymentioning

confidence: 99%

“…Most designs [7][8][9][10] develops a bandwidth-hungry approach and only use content SRAM to construct the second-level of memory hierarchy. On the other hand, Liu [5] and Hu [6] additionally include slice SRAM (or row-store buffer in [6]) to facilitate the memory accesses. Those SRAMs cache the decoded or neighboring pixels that are frequently used in next time for increasing the data reuse probability and improving memory performance.…”

Section: Memory Hierarchymentioning

confidence: 99%

“…Many memory-hierarchy-based designs of H.264/ AVC have been reported of the time [5][6][7][8][9][10]. However, they usually developed a bandwidth and/or memory capacity-starved design approaches without taking into account memory allocation and data locality issues.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Design of an H.264/AVC Decoder with Memory Hierarchy and Line-Pixel-Lookahead

Liu¹,

Lee²

2007

J Sign Process Syst Sign Image

Self Cite

View full text Add to dashboard Cite

Abstract. This paper describes a novel memory hierarchy and line-pixel-lookahead (LPL) for an H.264/AVC video decoder. The memory system is the bottleneck of most video processors, particularly in the newly announced H.264/AVC. This is because it utilizes the neighboring pixels to create a reliable predictor, leading to a dependency on a long past history of data. This problem can be resolved by allocating memory space but inducing large silicon area and power consumption as well. We first review the existing solutions and propose a three-level memory hierarchy with line-pixel-lookahead to improve access efficiency. Three-level memory hierarchy includes registers, content/slice SRAM and external frame DRAM. We emphasize the need to consider the secondary hierarchy, content/slice SRAM, during the design of an H.264/AVC decoder. Specifically, we introduce a slice SRAM and line-pixel-lookahead to lower the memory capacity and external bandwidth. This SRAM stores neighboring pixels and prevents the data re-access from DRAM. Linepixel-lookahead exploits multi-dimensional pixel locality so as to averagely improve prediction performance by 6.54% compared to conventional vertical prediction. Simulation results also reveal that the proposal makes a better trade-off between memory allocation and external bandwidth as well as power, leading to 50% of memory power reduction compared to the design without exploiting the secondary slice SRAM hierarchy.

show abstract

Section: Memory Hierarchymentioning

confidence: 99%

Section: Memory Hierarchymentioning

confidence: 99%

See 1 more Smart Citation

Design of an H.264/AVC Decoder with Memory Hierarchy and Line-Pixel-Lookahead

Liu¹,

Lee²

2007

J Sign Process Syst Sign Image

Self Cite

View full text Add to dashboard Cite

show abstract

“…Liu et al, [11] implement a H.264 decoder for mobile applications. To conserve power, they employ a 4 × 4 subblock level pipelining scheme, clock-gating, voltage scaling, and a three level memory hierarchy.…”

Section: Related Workmentioning

confidence: 99%

H.264 Decoder: A Case Study in Multiple Design Points

Fleming

Lin

Dave

et al. 2008

2008 6th ACM/IEEE International Conference on Formal Methods and Models for Co-Design

View full text Add to dashboard Cite

Abstract:H.264, a state-of-the-art video compression standard, is used across a range of products from cell phones to HDTV. These products have vastly different performance, power and cost requirements, necessitating different hardwaresoftware solutions for H.264 decoding. We show that a design methodology and associated tools which support synthesis from high-level descriptions and which allow modular refinement throughout the design cycle, can share the majority of design effort across multiple design points. Using Bluespec SystemVerilog, we have created a variety of designs for the H.264 decoder tuned to support decoding at resolutions ranging from QCIF video (176 × 144 @15 frames/second) to 1080p video (1280 × 1080)p @60 frames/second) in a 180nm process. Some of these design points require major transformations of pipelining to increase performance or to reduce area. We also explore several common design issues surrounding memory structures, such as caches and on-chip vs. off-chip memories.We believe the design methodology used in this paper is directly applicable to many IP blocks involving algorithmic specifications. The same design capabilities also permit rapid microarchitecture exploration and changes in RTL late in the design process even in non-algorithmic IP blocks.

show abstract

“…Improving the memory hierarchy or reducing the memory size is very effective for achieving low power dissipation because a memory system occupies about 70% of core power dissipation [2]. Figure 2 depicts a three-level memory hierarchy where a slice pixel SRAM is allocated for the storage with rows of pixels since H.264/AVC features to access logically adjacent pixels in the Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.…”

Section: Low-power Design Strategymentioning

confidence: 99%

Design of a 125μW, fully-scalable MPEG-2 and H.264/AVC video decoder for mobile applications

Liu

Chung

Lee

et al. 2006

Proceedings of the 43rd Annual Conference on Design Automation - DAC '06

Self Cite

View full text Add to dashboard Cite

A design of MPEG-2 and H.264/AVC video decoder is demonstrated in a 0.18µm CMOS [1]. The key design issues involved in this advanced IC are discussed, including improving area and power efficiency. Power dissipation is greatly lowered through the architectural exploration. Measurement results show that MPEG-2 and H.264/AVC real-time decoding of QCIF@15fps are achieved at 1.15MHz with power dissipation of 108µW and 125µW respectively at 1V supply voltage.

show abstract

An 865-μW H.264/AVC Video Decoder for Mobile Applications

Cited by 17 publications

References 8 publications

Design of an H.264/AVC Decoder with Memory Hierarchy and Line-Pixel-Lookahead

Design of an H.264/AVC Decoder with Memory Hierarchy and Line-Pixel-Lookahead

H.264 Decoder: A Case Study in Multiple Design Points

Design of a 125μW, fully-scalable MPEG-2 and H.264/AVC video decoder for mobile applications

Contact Info

Product

Resources

About