Design of a 125μW, fully-scalable MPEG-2 and H.264/AVC video decoder for mobile applications

Abstract

A design of MPEG-2 and H.264/AVC video decoder is demonstrated in a 0.18µm CMOS [1]. The key design issues involved in this advanced IC are discussed, including improving area and power efficiency. Power dissipation is greatly lowered through the architectural exploration. Measurement results show that MPEG-2 and H.264/AVC real-time decoding of QCIF@15fps are achieved at 1.15MHz with power dissipation of 108µW and 125µW respectively at 1V supply voltage.

Methods for Power/Throughput/Area Optimization of H.264/AVC Decoding

“…A more convincing processing cycle comparison of various granularities is described in Table 1 from [18]. Compared with the 4×4 block pipeline, the 16×16 MB pipeline improves the throughput by 26% at the cost of additional hardware.…”

“…Basically, what an optimal architecture should be depends on applications and the overall system considerations. The many methods can be roughly divided into three categories: general-purpose processors [3], DSP processors [4], and hardwired/ dedicated decoders [5][6][7][8][9][10][11][12][13][14]. Using a general purpose processor, it is difficult to achieve real-time performance even operating at a very high frequency since the general data path and sequential processing flow are not compatible with video processing.…”

“…Although designs of dedicated decoders have been discussed in [5][6][7][8][9][10][11][12][13][14], they are designed for specific applications. There is no work in literatures ever systematically studying the joint optimization of PTA and how to balance design tradeoff for different applications.…”

“…There is no work in literatures ever systematically studying the joint optimization of PTA and how to balance design tradeoff for different applications. Based on the design experience of several full-function chips [5][6][7][8][9], this paper proposes design methods and guidelines at both system and module levels for efficient video decoding under different application constraints.…”

A Multi-Standards HDTV Video Decoder for Blu-Ray Disc Standard

“…Semiconductor devices that meet these standards for multimedia applications are required to achieve high performance and cost effectiveness. Several solutions [1]- [3] are introduced; however, none of them corresponded for highcompression optical disc standards, such as Blu-ray. To develop a chip for practical use, hardware size, memory usage and memory access band width have to be considered.…”