Methods for Power/Throughput/Area Optimization of H.264/AVC Decoding

Xu, Ke; Liu, Tsu-Ming; Guo, Jiun-In; Choy, Chiu-Sing

doi:10.1007/s11265-009-0408-6

Cited by 11 publications

(4 citation statements)

References 19 publications

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“…In [16], the performance and energy consideration when using pipelines and parallelism in CMOS circuits is studied and it was shown why these architectures increase the energy efficiency. In [24], the particular case of H.264 video decoding is analyzed and an energy-aware architecture design methodology is proposed for energy efficient H.264/AVC decoding. At this level, the impact on the energy consumption of application and operating system layers are not considered.…”

Section: Related Workmentioning

confidence: 99%

DyPS

et al. 2014

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In addition to General Purpose Processors (GPP), Multicore SoCs equipping modern mobile devices contain specialized Digital Signal Processor designed with the aim to provide better performance and low energy consumption properties. However, the experimental measurements we have achieved revealed that system overhead, in case of DSP video decoding, causes drastic performances drop and energy efficiency as compared to the GPP decoding. This paper describes DyPS, a new approach for energy-aware processor switching (GPP or DSP) according to the video quality. We show the pertinence of our solution in the context of adaptive video decoding and describe an implementation on an embedded Linux operating system with the help of the GStreamer framework. A simple case study showed that DyPS achieves 30% energy saving while sustaining the decoding performance.

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Section: Related Workmentioning

confidence: 99%

DyPS

et al. 2014

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“…The complexity of the filtering process varies with video characteristics and bit-rate [20]. This variation comes into effect by the percentage of edges that are not filtered due to BS=0.…”

Section: Introductionmentioning

confidence: 99%

A Bit-Rate Aware Scalable H.264/AVC Deblocking Filter Using Dynamic Partial Reconfiguration

Khraisha

Lee

2011

J Sign Process Syst

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In H.264/AVC, a deblocking filter improves visual quality by reducing the presence of blocking artifacts in decoded video frames. The deblocking filter accounts for one third of the computational complexity of the decoder. This paper exploits the scalability on the hardware and the algorithmic level to synergize the performance and to reduce the computational complexity. First, we propose a modular deblocking filter architecture which can be scaled to adapt to the required computing capability for various bit-rates, resolutions, and frame rate of video sequences. The scalable architecture is based on FPGA using dynamic partial reconfiguration. This desirable feature of FPGAs makes it possible for different hardware configurations to be implemented during run-time. The proposed design can be scaled to filter up to four different edges simultaneously, resulting in significant reduction of total processing time. Secondly, our experiments show that significant reduction in computational complexity can be achieved by the increased presence of skipped macroblocks at lower bitrates, thus, avoiding redundant filtering operations. The implemented architecture is evaluated using the Xilinx Virtex-4 ML410 FPGA board. The design operates at a maximum frequency of 103 MHz. The reconfiguration is done through Internal Configuration Access Port (ICAP) to achieve maximum performance needed by real time applications.

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“…This is achieved thanks to the use of specialized processing units [11] which eliminate the power consumption related to instruction decoding and control logic characterizing GPP [12]. As a consequence, most modern smartphones are equipped with an HDIP that consumes less energy with respect to the real-time video decoding constraint [13] [14]. However, HDIPs are not flexible and are costly to implement, which generate a long time-to-market for new video codecs [15].…”

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confidence: 99%