A Very Fast Trace-Driven Simulation Platform for Chip-Multiprocessors Architectural Explorations

Elrabaa, Muhammad E. S.; Hroub, Ayman; Mudawar, Muhamed F.; Al-Aghbari, Amran; Al-Asli, Mohammed; Khayyat, Ahmad

doi:10.1109/tpds.2017.2713782

Cited by 6 publications

(4 citation statements)

References 19 publications

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“…Floating-point units can be shared among the cores, where the degree of sharing is an architecture parameter, depending on the area and power constraints. A standard interface, named HWPE 5 [23], allows to include specific hardware accelerators 5 https://hwpe-doc.readthedocs.io/en/latest/ in the PULP CL domain, sharing L1 memory (i.e., the TCDM) with general-purpose cores.…”

Section: Target Architecturementioning

confidence: 99%

“…In contrast, the fastest simulators typically simulate only the functionalities of a system but without timing and performance information [4]. In the middle, several simulators provide reasonable fast simulation and accuracy but typically without simulating the entire system and the possibility to quickly explore a range of different configurations, crucial for DSE [5].…”

Section: Introductionmentioning

confidence: 99%

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GVSoC: A Highly Configurable, Fast and Accurate Full-Platform Simulator for RISC-V based IoT Processors

Bruschi,

Haugou,

Tagliavini

et al. 2022

Preprint

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The last few years have seen the emergence of IoT processors: ultra-low power systems-on-chips (SoCs) combining lightweight and flexible micro-controller units (MCUs), often based on open-ISA RISC-V cores, with application-specific accelerators to maximize performance and energy efficiency. Overall, this heterogeneity level requires complex hardware and a fullfledged software stack to orchestrate the execution and exploit platform features. For this reason, enabling agile design space exploration becomes a crucial asset for this new class of lowpower SoCs. In this scenario, high-level simulators play an essential role in breaking the speed and design effort bottlenecks of cycle-accurate simulators and FPGA prototypes, respectively, while preserving functional and timing accuracy. We present GVSoC, a highly configurable and timing-accurate event-driven simulator that combines the efficiency of C++ models with the flexibility of Python configuration scripts. GVSoC is fully opensourced, with the intent to drive future research in the area of highly parallel and heterogeneous RISC-V based IoT processors, leveraging three foundational features: Python-based modular configuration of the hardware description, easy calibration of platform parameters for accurate performance estimation, and high-speed simulation. Experimental results show that GVSoC enables practical functional and performance analysis and design exploration at the full-platform level (processors, memory, peripherals and IOs) with a speed-up of 2500× with respect to cycle-accurate simulation with errors typically below 10% for performance analysis.

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Section: Target Architecturementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

GVSoC: A Highly Configurable, Fast and Accurate Full-Platform Simulator for RISC-V based IoT Processors

Bruschi,

Haugou,

Tagliavini

et al. 2022

Preprint

View full text Add to dashboard Cite

show abstract

“…It is very hard for trace driven simulators to model the run-time changes in the behavior of multi-threaded applications [60], [61]. However, lately, few research works have been put forward to efficiently use trace-driven simulators for multi-threaded workloads, [65], [66].…”

Section: ) Trace-driven Simulatorsmentioning

confidence: 99%

A Survey of Computer Architecture Simulation Techniques and Tools

Akram

Sawalha

2019

IEEE Access

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Computer architecture simulators play an important role in advancing computer architecture research. With wider research directions and the increased number of simulators that have been developed, it becomes harder to choose a particular simulator to use. This paper reviews the fundamentals of different computer architecture simulation techniques. It also surveys many computer architecture simulators and classifies them into different groups based on their simulation models. Comparing computer architecture simulators with each other and validating their accuracy have been demanding tasks for architects. In addition to providing a survey of computer architecture simulation tools, we measured the experimental error of six contemporary computer architecture simulators: gem5, MARSSx86, Multi2Sim, PTLsim, Sniper, and ZSim. We also performed a detailed comparison of these simulators based on other features such as flexibility and micro-architectural details. We believe that this paper will be a very useful resource for the computer architecture community especially for early-stage computer architecture and systems researchers to gain exposure to the existing architecture simulation options.

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“…A trace-driven simulation framework for multi-processors using FPGA is presented in [25]. The simulator's input is a specially developed compact execution trace (CET) of the application.…”

Section: A Performance Models On Fpgasmentioning

confidence: 99%

Designing Application-Specific Heterogeneous Architectures from Performance Models

Cong

Charot

2019

2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip (MCSoC)

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In this paper, we propose an approach for designing application-specific heterogeneous systems based on performance models through combining accelerator and processor core models. An application-specific program is profiled by the dynamic execution trace and is used to construct a data flow model of the accelerator. Modeling of the processor is partitioned into an instruction set architecture (ISA) execution and a microarchitecture specific timing model. These models are implemented on FPGAs to take advantage of their parallelism and speed up the simulation when architecture complexity increases. This approach aims to ease the design of multi-core multi-accelerator architecture, consequently contributes to explore the design space by automating the design steps. A case study is conducted to confirm that presented design flow can model the accelerator starting from an algorithm, validate its integration in a simulation framework, allowing precise performance to be estimated. We also assess the performance of our RISC-V single-core and RISC-V-based heterogeneous architecture models.

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A Very Fast Trace-Driven Simulation Platform for Chip-Multiprocessors Architectural Explorations

Cited by 6 publications

References 19 publications

GVSoC: A Highly Configurable, Fast and Accurate Full-Platform Simulator for RISC-V based IoT Processors

GVSoC: A Highly Configurable, Fast and Accurate Full-Platform Simulator for RISC-V based IoT Processors

A Survey of Computer Architecture Simulation Techniques and Tools

Designing Application-Specific Heterogeneous Architectures from Performance Models

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