A Survey of Computer Architecture Simulation Techniques and Tools

Akram, Ayaz; Sawalha, Lina

doi:10.1109/access.2019.2917698

Cited by 69 publications

(36 citation statements)

References 118 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…Since Desikan's work, several simulators have been created along a validation effort to evaluate their accuracy. In Akram et al's research, 31 the authors evaluated and compared the gem5, 32 Multi2Sim, 33 MARSSx86, 34 PTLsim, 35 Sniper, 6 and ZSim 5 simulators. After thorough characterization of the simulators, the authors tested single core and multiprogrammed workloads on each simulator.…”

Section: Related Workmentioning

confidence: 99%

Investigating memory prefetcher performance over parallel applications: From real to simulated

Girelli

Moreira

Serpa

et al. 2021

Concurrency and Computation

View full text Add to dashboard Cite

Memory prefetcher algorithms are widely used in processors to mitigate the performance gap between the processors and the memory subsystem. The complexities behind the architectures and prefetcher algorithms, however, not only hinder the development of accurate architecture simulators, but also hinder understanding the prefetcher's contribution to performance, on both a real hardware and in a simulated environment. In this paper, we contribute to shed light on the memory prefetcher's role in the performance of parallel High‐Performance Computing applications, considering the prefetcher algorithms offered by both the real hardware and the simulators. We performed a careful experimental investigation, executing the NAS parallel benchmark (NPB) on a real Skylake machine, and as well in a simulated environment with the ZSim and Sniper simulators, taking into account the prefetcher algorithms offered by both Skylake and the simulators. Our experimental results show that: (i) prefetching from the L3 to L2 cache presents better performance gains, (ii) the memory contention in the parallel execution constrains the prefetcher's effect, (iii) Skylake's parallel memory contention is poorly simulated by ZSim and Sniper, and (iv) Skylake's noninclusive L3 cache hinders the accurate simulation of NPB with the Sniper's prefetchers.

show abstract

Section: Related Workmentioning

confidence: 99%

Investigating memory prefetcher performance over parallel applications: From real to simulated

Girelli

Moreira

Serpa

et al. 2021

Concurrency and Computation

View full text Add to dashboard Cite

show abstract

“…Prior work has surveyed many existing simulators [23], [24], with classifications based on traditional usage within the computer architecture research community as well as through an educational and pedagogical point of view [25]- [27], with some surveys proposing criteria for the evaluation of their suitability for teaching courses in computer architecture. Within the proposed criteria, the generator-based approach demonstrated in this work would be considered under the "Advanced Architecture (AA)" category with "Design Support.…”

Section: Generator-based Hardware Designmentioning

confidence: 99%

Vertically Integrated Computing Labs Using Open-Source Hardware Generators and Cloud-Hosted FPGAs

Amid

Asanović

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

View full text Add to dashboard Cite

The design of computing systems has changed dramatically over the past decade, but most courses in advanced computer architecture remain unchanged. Computer architecture education lies at the intersection between computer science and electrical engineering, with practical exercises in classes based on appropriate levels of abstraction in the computing system design stack. Hardware-centric lab exercises often require broad infrastructure resources and tend to navigate around tedious practical implementation concepts, while software-centric exercises leave a gap between modeling and system implementation implications that students later need to overcome in professional settings. Vertical integration trends in domain-specific compute systems, as well as software-hardware co-design, are often covered in classroom lectures, but are not reflected in laboratory exercises due to complex tooling and simulation infrastructure. We describe our experiences with a joint hardware-software approach to exploring computer architecture concepts in class exercises, by using opensource processor hardware implementations, generator-based hardware design methodologies, and cloud-hosted FPGAs. This approach further enables scaling course enrollment, remote learning and a cross-class collaborative lab ecosystem, creating a connecting thread between computer science and electrical engineering experience-based curricula.

show abstract

“…It was demonstrated by [10] that proper validation and calibration of simulator is very important for its accuracy. Accuracy evaluation made during this study showed that the least error in accuracy is achieved by simulators Sniper and ZSim, which have been validated against real hardware.…”

Section: Related Workmentioning

confidence: 99%

Implementation of Memory Subsystem of Cycle-Accurate Application-Level Simulator of the Elbrus Microprocessors

Порошин¹,

Знаменский²,

Meshkov³

2020

Proceedings of ISP RAS

View full text Add to dashboard Cite

Performance characteristics of any modern microprocessor largely depend on its memory subsystem. Naturally, the memory subsystem software model is an important component of the cycle-accurate simulator, and its validity and quality have high impact on the overall accuracy of the simulation. In this paper the cycleaccurate application-level simulator of the Elbrus microprocessor family is introduced. The structure of the cycle-accurate simulator is briefly explained. After that the software model of memory subsystem and its integration as a part of the cycle-accurate application-level simulator are described. We evaluate accuracy of the application-level cycle-accurate simulator on the SPEC CPU2006 benchmark and analyze the simulation errors. Finally, a brief comparison of different Elbrus architecture simulators is given.

show abstract

A Survey of Computer Architecture Simulation Techniques and Tools

Cited by 69 publications

References 118 publications

Investigating memory prefetcher performance over parallel applications: From real to simulated

Investigating memory prefetcher performance over parallel applications: From real to simulated

Vertically Integrated Computing Labs Using Open-Source Hardware Generators and Cloud-Hosted FPGAs

Implementation of Memory Subsystem of Cycle-Accurate Application-Level Simulator of the Elbrus Microprocessors

Contact Info

Product

Resources

About