Global software development (GSD) is continuously increasing because of many factors such as high quality software production in offshore destinations with significant cost-savings. Objective -The objective of this study is to identify the challenges of the existing tools used in GSD projects. Method -The authors applied the systematic literature review (SLR) approach and a survey-based empirical study approach to address the research objective. Results -From both data sets, the authors identified eight challenges of the existing tools used in GSD projects. The top-ranked challenges in the SLR are the 'inappropriate use of synchronous and asynchronous communication tools' and 'difficulties in adopting and learning to use the existing tools'. The top-ranked challenges in the questionnaire-based empirical study are the 'lack of awareness of existing tools used in GSD projects' and the 'lack of support for collaboration and group decision making'. The results show a weak negative correlation between the ranks obtained from the SLR and the questionnaire-based empirical study ((r s (8) = −0.313), p = 0.450) Conclusion: GSD organisations should address the challenges of the existing tools used in GSD projects, especially the most common ones.
The Standard Test Interface Language (STIL) is the de-facto standard for transferring test data between the test generation environment and the test equipment. STIL's°exibility and extensibility facilitates its use as the sole input language for automatic test-pattern generation (ATPG). However, STIL format is complex and does not provide support for algorithmic interactive testing which necessitate the use of additional programming languages to do that. In this paper, we propose a new Test De¯nition Language for Integrated Circuits (TDLIC) based on the Extensible Markup Language (XML). TDLIC is a description language for de¯ning tests of digital ICs in a precise and reusable form. The proposed TDLIC provides a common platform for specifying test data as well as complex test procedures. A case study that includes a validation platform is used to show the full capabilities of TDLIC. The validation platform is an FPGA-based system that emulates the automatic test equipment and a prototype IC with four circuits to be tested.
Requiring no functional simulation, trace-driven simulation has the potential of achieving faster simulation speeds than execution-driven simulation of multicore architectures. An efficient, on-the-fly, high-fidelity trace generation method for multithreaded applications is reported. The generated trace is encoded in an instruction-like binary format that can be directly "interpreted" by a timing simulator to simulate a general load/store or x8-like architecture. A complete tool suite that has been developed and used for evaluation of the proposed method showed that it produces smaller traces over existing trace compression methods while retaining good fidelity including all threading-and synchronization-related events.
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