A Versatile Non-Overlapping Signal Generator for Efficient Power-Converters Operation

Karimi, Mousa; Ali, Mohamed; Nabavi, Morteza; Hassan, Ahmad; Amer, Mostafa; Gosselin, B

doi:10.1109/iscas45731.2020.9180718

Cited by 9 publications

(9 citation statements)

References 12 publications

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“…To minimize shoot-through induced losses, the overlap of PMOS and NMOS drivers on periods during the transitions should be minimized. This can be achieved by employing non-overlapping circuit configurations, which generate two non-overlapped signals to drive the power transistors [20], [21]. Also, suitably designed distinct driving circuits for PMOS and NMOS transistors may help eliminate shootthrough current [22].…”

Section: A Class-d Power Amplifiermentioning

confidence: 99%

A Versatile SoC/SiP Sensor Interface for Industrial Applications: Implementation Challenges

et al. 2022

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We present in this paper design considerations and implementation challenges of a proposed versatile SoC/SiP sensor interface intended for industrial applications. The proposed interface involves high-voltage circuits such as class-D power amplifiers, gate drivers, level shifters, and electrical isolators. Also, it includes low-voltage blocks like programmable gain amplifiers and ADCs. In addition, DC-to-DC converters are used to supply the various building blocks of the projected sensor interface. The key challenges for implementing each block are discussed in this paper. Also, the technological aspects to support the proposed SoC/SiP solution are given. Moreover, the different available packaging technologies to implement the intended SiP solution are discussed in addition to the thermal aspects associated with the system packaging.INDEX TERMS Industrial applications, sensor interface, versatility, system-on-chip (SoC), system-inpackage (SiP), thermal management. Author et al.: Preparation of Papers for IEEE TRANSACTIONS and JOURNALS TABLE 1. Performance Comparison of High-Voltage and High-Power Class-D Power Amplifiers. YVES AUDET (Member, IEEE) received the B.Sc. degree and the M.Sc. degree in physics from the

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Section: A Class-d Power Amplifiermentioning

confidence: 99%

A Versatile SoC/SiP Sensor Interface for Industrial Applications: Implementation Challenges

et al. 2022

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“…The propagation delay of these inverters provides the delays in the non-overlapping signals. This configuration of integrated circuits produces typical picosecond delays and is thus not useful in various power applications requiring long delays in the range of nanoseconds (e.g., high-voltage circuits, high currents, and highly reactive loads) [32].…”

Section: Proposed Dead-time Circuitmentioning

confidence: 99%

“…In other cases, time constants are used and implemented with resistors, capacitors, current sources, etc. [32]. The latter is preferred for high voltage applications that require long delays [33].…”

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confidence: 99%

An Active Dead-Time Control Circuit With Timing Elements for a 45-V Input 1-MHz Half-Bridge Converter

Karimi

Ali

Hassan

et al. 2022

IEEE Trans. Circuits Syst. I

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In this study, a dead-time control circuit is proposed to generate independent delays for the high and low sides of halfbridge converter switches. In addition to greatly decreasing the losses of power converters, the proposed method mitigates the shoot-through current through the application of superimposed power switches. The circuit presented here comprises a switched capacitor architecture and is implemented in AMS 0.35 µm technology. In the implementation, the proposed dead-time control circuit occupies a silicon area of 70 µm × 180 µm. To realize the technique, a two-sided wide swing current source is employed. Each sides of the current source comes with two capacitors, two Schmitt triggers, and three transmission gates. Results show that the low and high sides of the projected half-bridge converter switches respectively require delays of 35 and 62 ns. The performance of the proposed dead-time circuit is evaluated by assembling it with the half-bridge converter. The proposed dead-time prototype achieves a 40% drop in power losses in the half-bridge circuit.

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“…SoCs frequently use multiple voltage supply and signal levels inside their various building blocks [15]- [18]. Using multiple technologies operating at various supply voltages within the same SiP can decrease fabrication cost and power consumption [19]- [21].…”

Section: Introductionmentioning

confidence: 99%

A 7.6-ns Delay Subthreshold Level-Shifter Leveraging a Composite Transistor and a Voltage-Controlled Current Source

et al. 2022

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A novel level shifter (LS) circuit that uses a new low-power approach based on a parasitic capacitance voltage controlled current source is presented to minimize the propagation delay (PD) and maximize the voltage conversion range. This new scheme uses a simplified circuit including a dependent current source, a composite transistor made of three interconnected n-channel MOSFETs (TnM), one CMOS input inverter, and one CMOS output buffer to provide a fast response time. The circuit utilizes the combined action of the equivalent parasitic capacitance of the TnM, the value of which changes dynamically according to the transient value of the input voltage, and the dependent current source to shift the input signal level up from subthreshold voltage levels to +3.0 V, with minimal delay and power consumption. The LS circuit fabricated in 0.35 µm CMOS technology occupies a silicon area of only 25 µm×25 µm. The LS shows measured rising and falling PDs of, respectively, 4 and 11.2 ns. The measured results show that the presented circuit outperforms other solutions over a wide frequency range of 1 to 130 MHz. The fabricated circuit consumes a static power 31.5 pW and a dynamic power of 3.4 pJ per transition at 1 kHz, VDDL=0.8 V, and a capacitive load of CL=0.1 pF.

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A Versatile Non-Overlapping Signal Generator for Efficient Power-Converters Operation

Cited by 9 publications

References 12 publications

A Versatile SoC/SiP Sensor Interface for Industrial Applications: Implementation Challenges

A Versatile SoC/SiP Sensor Interface for Industrial Applications: Implementation Challenges

An Active Dead-Time Control Circuit With Timing Elements for a 45-V Input 1-MHz Half-Bridge Converter

A 7.6-ns Delay Subthreshold Level-Shifter Leveraging a Composite Transistor and a Voltage-Controlled Current Source

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