An Active Dead-Time Control Circuit With Timing Elements for a 45-V Input 1-MHz Half-Bridge Converter

Abstract

In this study, a dead-time control circuit is proposed to generate independent delays for the high and low sides of halfbridge converter switches. In addition to greatly decreasing the losses of power converters, the proposed method mitigates the shoot-through current through the application of superimposed power switches. The circuit presented here comprises a switched capacitor architecture and is implemented in AMS 0.35 µm technology. In the implementation, the proposed dead-time control circuit occupies a silicon area of 70 µm × 180 µm. To realize the technique, a two-sided wide swing current source is employed. Each sides of the current source comes with two capacitors, two Schmitt triggers, and three transmission gates. Results show that the low and high sides of the projected half-bridge converter switches respectively require delays of 35 and 62 ns. The performance of the proposed dead-time circuit is evaluated by assembling it with the half-bridge converter. The proposed dead-time prototype achieves a 40% drop in power losses in the half-bridge circuit.

Delay Mismatch Insensitive Dead Time Generator for High-Voltage Switched-Mode Power Amplifiers

“…In addition, switched-mode PAs suffer from the shoot-through currents that happen when their high-side and low-side power transistors are conducting at the same time. Such currents degrade their efficiency and pose safety concerns [9], [10], [11].…”

“…During this overlapping time interval, the two power MOSFETs are ON and a shoot-through current flows from the HV power supply to the ground. This current leads to a very high power consumption and can potentially burn the circuit [6], [9], [10]. To prevent shoot-through currents, the input signal to the HSGD and LSGD can be split by a dead time generator (DTG) into two signals with a dead time between their respective active periods during which both transistors are OFF as shown in Fig.…”

“…Other implementations use passive components and comparators to generate the dead time [18], or use senseFETs to detect the body-diode conduction followed by comparators and digital circuits to adjust the dead time [13]. The works presented in [10] and [19] propose an adjustable dead time generator using a structure composed of current sources and switched capacitors, while the work in [20] uses analog comparators and a digitally-controlled delay cell to adjust the dead time. Some of the reported designs use passive devices and analog components that are highly susceptible to noise.…”

“…Other designs are implemented in lowvoltage technology, and hence require scaling and adaptation to properly operate in the HV domain. The negative effects of PVT variations on the gate drivers' delay mismatch and the generated dead time were considered in previous works such as [9], [10], [18], and [19]. These effects were mitigated in such works, either by externally calibrating the dead time generator, or by accounting for them through corner simulations.…”