A variable-stress shallow trench isolation (STL) technology with diffused sidewall doping for submicron CMOS

Davari, B.; Koburger, Charles W.; Furukawa, Toshio; Taur, Yuan; Noble, W.; Megdanis, A.C.; Warnock, J.; Mauer, J. L.

doi:10.1109/iedm.1988.32759

Cited by 46 publications

(10 citation statements)

References 4 publications

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“…On the other hand, the isolation technology has shifted from the conventional LOCOS to the shallow trench isolation (STI) [3] as the technology nodes have been scaled down to submicron area, and the comparison of the device reliability dependent on the isolation technologies have been reported [4][5][6]. It is expected that the STI technology may modulate the high electric fields near the channelwidth edge resulting in the reliability variation along the channel-width direction, because the narrow-width or the inverse-narrow-width effects are largely influenced by the STI process [7,8].…”

Section: Introductionmentioning

confidence: 99%

A test structure to separately analyze CMOSFET reliabilities around center and edge along the channel width

Ohzone

Ishii

Morishita

et al. 2006

2006 IEEE International Conference on Microelectronic Test Structures

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A test structure with four kinds of MOSFETs(i.e., [A]([D]) with a short(long) channel-length all over the channel width, [B]([C]) with the short(long) and the long(short) channel-length around the center and the both isolation-edges, respectively) was proposed to separately analyze the location where the hot-carrierinduced CMOSFET reliability is determined around the center or the isolation-edge along the channelwidth. The reliability data were almost categorized into three (i.e., [A], [B]/[C] and [D]), which mean that the reliabilities are nearly the same around center or isolation-edge for the CMOSFETs.

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Section: Introductionmentioning

confidence: 99%

A test structure to separately analyze CMOSFET reliabilities around center and edge along the channel width

Ohzone

Ishii

Morishita

et al. 2006

2006 IEEE International Conference on Microelectronic Test Structures

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“…A significant problem associated with most isolation techniques, such as local isolation of Silicon ͑LOCOS͒, mesa isolation, and shallow trench isolation ͑STI͒, is the presence of parasitic edge transistors in N-channel metal-oxide-semiconductor field effect transistors ͑MOSFETs͒. [1][2][3][4][5] As seen in Fig. 1, these edge devices locate along the edges of the active device region and have a threshold voltage lower than that of the ideal main transistor.…”

Section: Introductionmentioning

confidence: 99%

“…5 A sidewall boron doping step is usually performed before oxidation steps in both LOCOS and STI to suppress the edge transistor effects. 11 A dielectric isolation technology, which uses the selective epitaxial growth ͑SEG͒ technique, has been developed ͑Fig. 3͒.…”

Section: Introductionmentioning

confidence: 99%

Edge transistor elimination in oxide trench isolated N-channel metal–oxide–semiconductor field effect transistors

Yang

Denton

Neudeck

2001

Journal of Vacuum Science &Amp; Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena

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Articles you may be interested inStrain response of high mobility germanium n-channel metal-oxide-semiconductor field-effect transistors on (001) substrates Appl. Phys. Lett. 99, 022106 (2011); 10.1063/1.3604417 A model for radiation-induced off-state leakage current in N-channel metal-oxide-semiconductor transistors with shallow trench isolation Dependence of power trench metal-oxide-semiconductor field-effect transistor processes on wafer thickness Nanopatterning of epitaxial Co Si 2 using oxidation in a local stress field and fabrication of nanometer metaloxide-semiconductor field-effect transistors J. Appl. Phys. 96, 5775 (2004); 10.1063/1.1808246 Nanometer patterning of epitaxial CoSi 2 /Si(100) for ultrashort channel Schottky barrier metal-oxide-semiconductor field effect transistors Bulk N-channel metal-oxide-semiconductor field effect transistors ͑MOSFETs͒ can suffer from parasitic edge transistor effects, unless several extra processing and masking steps are used. These edge devices increase the off-state current and degrade subthreshold slope of the N-MOSFETs. Parasitic edge transistors in oxide trench isolated N-MOSFETs, formed using selective epitaxial growth of silicon, were caused by the boron out-diffusion during high temperature process steps. Employing a simple ammonia nitridation of the field oxide before the epitaxial growth step, boron out-diffusion into the surrounding oxide was suppressed. The parasitic edge transistors in oxide trench isolated N-MOSFETs were eliminated.

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“…Various approaches were proposed to reduce these undesirable edge effects, e.g. 1) additional trench sidewall doping by either trench sidewall implant [2] or diffusion [3], 2) a T-shaped refill-oxide trench isolation structure [4], 3) an oxide-poly-oxide field-shield on the trench sidewall together with chemical-mechanical polish (CMP) to avoid sidewall oxide loss [5], and 4) a trench-after-gate process to avoid sidewall oxide loss [6]. However, trench sidewall doping is undesiiable for scaled devices of which the device width is comparable to twice the diffusion depth of the sidewall doping.…”

Section: Introductionmentioning

confidence: 99%

“…Besides the associated process complexity (and thus the higher manufacturing cost) and the successful scaling of LOCOStype isolation to 0.25pm technology node [7], trench isolation by oxide refill has long been noted to have trench edge enhanced electric field effects, resulting from the over-etch of trench lining oxide. Typical edge effects include subthreshold double hump phenomena [3,6] or inverse narrow width effects [Z]. Various approaches were proposed to reduce these undesirable edge effects, e.g.…”

Section: Introductionmentioning

confidence: 99%

A trench isolation study for deep submicron CMOS technology

Chen

Rödder

Chatterjee

et al.

1993 International Symposium on VLSI Technology, Systems, and Applications Proceedings of Technical Papers

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A b s t r a c tThe simple approach of thermal oxide capped poly refill trench isolation [l] is studied with regard to the impact of cap oxide thickness, trench wall thermal oxide thickness, and trench depth on MOSFET and isolation characteristics. It is shown that an increase of cap oxide thickness (to=) from 600 to 2OOOA eliminates subthreshold double-hump phenomena, improves isolation VT, improves inverse narrow-width effect, and still maintains reasonably low diode leakage current. An improvement of isolation VT is observed with thinner thermal oxide (-50A) on trench wall due to the less dopant segregation, while diode leakage is found to be insensitive to the trench wall thermal oxide thickness. The trade-off between latch-up holding and MOSFET snapback voltages leads to an optimal trench depth. I n t r o d u c t i o nTrench isolation has long been regarded as a successor to LOCOS (Local Oxidation of Silicon) type isolation due to its relatively smaller physical encroachment (or bird's beak), larger isolation distance (due to trench depth), and higher latch-up immunity compared to those of a LOCOS-type isolation [l-71. However, as yet, trench isolation has hardly been used in CMOS products despite these advantages. Besides the associated process complexity (and thus the higher manufacturing cost) and the successful scaling of LOCOStype isolation to 0.25pm technology node [7], trench isolation by oxide refill has long been noted to have trench edge enhanced electric field effects, resulting from the over-etch of trench lining oxide. Typical edge effects include subthreshold double hump phenomena [3,6] or inverse narrow width effects [Z]. Various approaches were proposed to reduce these undesirable edge effects, e.g. 1) additional trench sidewall doping by either trench sidewall implant [2] or diffusion [3], 2) a T-shaped refill-oxide trench isolation structure [4], 3) an oxide-poly-oxide field-shield on the trench sidewall together with chemical-mechanical polish (CMP) to avoid sidewall oxide loss [5], and 4) a trench-after-gate process to avoid sidewall oxide loss [6]. However, trench sidewall doping is undesiiable for scaled devices of which the device width is comparable to twice the diffusion depth of the sidewall doping. Both the T-shaped refill-oxide and the oxide-polyoxide field-shield plus CMP planarization process are quite complicated. The trench-after-gate process may damage the gate oxide quality. In this study, we revisit the simple thermal oxide capped poly refill trench isolation process [l] and investigate the impacts of cap oxide thickness, trench wall thermal oxide thickness, and trench depth on MOSFET and isolation Characteristics.S a m p l e P r e p a r a t i o n a n d Characterization A 0.4pm CMOS technology is used to study the oxidecapped poly-refilled trench isolation. The starting material waa p t y p e 2-5x 1015 cm-3 (100)-oriented non-epi Si wafer. After CM05 well formation, apodified scaled LOCOS with 5500A field oxide was formed for isolating active regions >.8pm apart. After a 15...

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A variable-stress shallow trench isolation (STL) technology with diffused sidewall doping for submicron CMOS

Cited by 46 publications

References 4 publications

A test structure to separately analyze CMOSFET reliabilities around center and edge along the channel width

A test structure to separately analyze CMOSFET reliabilities around center and edge along the channel width

Edge transistor elimination in oxide trench isolated N-channel metal–oxide–semiconductor field effect transistors

A trench isolation study for deep submicron CMOS technology

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