A trench isolation study for deep submicron CMOS technology

Abstract

A b s t r a c tThe simple approach of thermal oxide capped poly refill trench isolation [l] is studied with regard to the impact of cap oxide thickness, trench wall thermal oxide thickness, and trench depth on MOSFET and isolation characteristics. It is shown that an increase of cap oxide thickness (to=) from 600 to 2OOOA eliminates subthreshold double-hump phenomena, improves isolation VT, improves inverse narrow-width effect, and still maintains reasonably low diode leakage current. An improvement of isolation VT is observed with thinner thermal oxide (-50A) on trench wall due to the less dopant segregation, while diode leakage is found to be insensitive to the trench wall thermal oxide thickness. The trade-off between latch-up holding and MOSFET snapback voltages leads to an optimal trench depth. I n t r o d u c t i o nTrench isolation has long been regarded as a successor to LOCOS (Local Oxidation of Silicon) type isolation due to its relatively smaller physical encroachment (or bird's beak), larger isolation distance (due to trench depth), and higher latch-up immunity compared to those of a LOCOS-type isolation [l-71. However, as yet, trench isolation has hardly been used in CMOS products despite these advantages. Besides the associated process complexity (and thus the higher manufacturing cost) and the successful scaling of LOCOStype isolation to 0.25pm technology node [7], trench isolation by oxide refill has long been noted to have trench edge enhanced electric field effects, resulting from the over-etch of trench lining oxide. Typical edge effects include subthreshold double hump phenomena [3,6] or inverse narrow width effects [Z]. Various approaches were proposed to reduce these undesirable edge effects, e.g. 1) additional trench sidewall doping by either trench sidewall implant [2] or diffusion [3], 2) a T-shaped refill-oxide trench isolation structure [4], 3) an oxide-poly-oxide field-shield on the trench sidewall together with chemical-mechanical polish (CMP) to avoid sidewall oxide loss [5], and 4) a trench-after-gate process to avoid sidewall oxide loss [6]. However, trench sidewall doping is undesiiable for scaled devices of which the device width is comparable to twice the diffusion depth of the sidewall doping. Both the T-shaped refill-oxide and the oxide-polyoxide field-shield plus CMP planarization process are quite complicated. The trench-after-gate process may damage the gate oxide quality. In this study, we revisit the simple thermal oxide capped poly refill trench isolation process [l] and investigate the impacts of cap oxide thickness, trench wall thermal oxide thickness, and trench depth on MOSFET and isolation Characteristics.S a m p l e P r e p a r a t i o n a n d Characterization A 0.4pm CMOS technology is used to study the oxidecapped poly-refilled trench isolation. The starting material waa p t y p e 2-5x 1015 cm-3 (100)-oriented non-epi Si wafer. After CM05 well formation, apodified scaled LOCOS with 5500A field oxide was formed for isolating active regions >.8pm apart. After a 15...