Nanoscale Accumulated Body Si nMOSFETs

Temperature Dependent Characteristics and Electrostatic Threshold Voltage Tuning of Accumulated Body MOSFETs

“…The narrow-channel accumulated body nMOSFETs were fabricated using a conventional bulk silicon process, with additional steps to form the p+ doped side-gate structure and its contact. The side-gate structure is formed around the body using a side-wall process [44], [62]. The side-gate contact is formed in the same etch step by using a lithographically defined region slightly offset from the active region.…”

“…The body is doped with 1×10 17 cm -3 boron, the side-gate with 1×10 20 cm -3 boron, the source and drain with 1×10 20 cm -3 phosphorous using ion-implantation. Details of the device fabrication, room temperature electrical characterization and simulation results, including high temperature behavior, can be found in [43], [44], and [62].…”

“…The body/side-oxide interfaces of these devices are in accumulation, even with Vside = 0 V since the side gates are p+ doped (unlike [40], [41]), thus suppressing recombination at the interface defects, blocking interface leakage currents, and reducing the depletion depth under the active region. Negative bias on the side-gate increases the hole concentration at the side-interfaces, shrinks the depletion depth further, increasing the electrostatic control of the body and suppressing control of the drain potential on the source barrier [41], [44], hence, improving DIBL and SS and increasing Vt.…”