CMOS shallow-trench-isolation to 50-nm channel widths

VanDerVoom, P.; Gan, Dong; Krusius, J.P.

doi:10.1109/16.842959

Cited by 13 publications

(7 citation statements)

References 14 publications

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“…The degradation in device characteristics due to diffusion of the dopants, introduced at the device periphery, is more significant for nMOSFET devices as boron is used as the primary p-type dopant in silicon devices. Electrostatic control of the threshold voltage at the device edges via an independently controlled side-gate, surrounding the active area of the device is a viable method to suppress the edge-related leakage currents in order to achieve the required low power CMOS performance with low leakage currents [6,7] (Fig.1).…”

Section: Discussionmentioning

confidence: 99%

A Silicon Nitride Based Shallow Trench Isolation with Side-Gate for CMOS Integration with MEMS Components for System-On-Chip Applications

Gokirmak

Tiwari

2004

MRS Proc.

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We have developed a hydrofluoric acid (HF) resistant, composite shallow trench isolation (STI) process for MOSFETs utilizing silicon nitride as isolation material for on-chip integration of micro-electro-mechanical (MEMS) resonators and CMOS devices. Peripheral leakage currents in silicon nitride isolated MOSFETs are suppressed by employing an independently controlled polysilicon side-gate, surrounding the active area of the devices. Electrostatic control of the threshold voltage at the device periphery alleviates the need for edge implants, resulting in increased thermal budget. Compatibility with HF release processes and high temperature anneal cycles allows integration of MEMS components in close proximity to CMOS devices for system-on-chip applications. nMOSFET devices fabricated using this composite STI process show excellent device characteristics.

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Section: Discussionmentioning

confidence: 99%

A Silicon Nitride Based Shallow Trench Isolation with Side-Gate for CMOS Integration with MEMS Components for System-On-Chip Applications

Gokirmak

Tiwari

2004

MRS Proc.

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“…Shallow Trench Isolation(STI) is a device isolation technique for integrated circuits. As the semiconductor industry moved to sub 0.25um CMOS technology there is a need for creating very small void free gaps on the wafer sub-layer [1,2,3,4] . STI is a mainstream isolation method for advanced logic, DRAM, SRAM and flash memory.…”

Section: Introductionmentioning

confidence: 99%

A Robust Shallow Trench Isolation High Density Plasma Chemical Vapor Deposition Void Free Process for 0.13μm CMOS Technology

Ning¹,

Lin

Xing

et al. 2011

ECS Trans.

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Shallow Trench Isolation(STI) is widely used in advanced CMOS technologies. This paper describes a shallow trench isolation for 0.13μm CMOS technologies development which utilizes AMAT Ultima Plus High Density Plasma (HDP) CVD oxide process to fill 0.18μm wide and 0.5μm deep trenches with void free. Through optimizing source/bias RF power, process gas flow and cross section verification, as a result, we got a robust gap-fill recipe with void free.

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“…Shallow trench isolation (STI) has become the inevitable solution to isolate devices in next generation CMOS technology due to its superior isolation capability and topology [1][2][3]. However, STI also results in a rougher surface and small defects around the top corner of the active area, which in turn cause issues such as a 'double hump' in I d −V gs curves, inverse narrow width effect (INWE) and enhancement of local junction leakage [4,5].…”

Section: Introductionmentioning

confidence: 99%

A novel STI etching technology to mitigate an inverse narrow width effect, and improve device performances for 90 nm node and beyond CMOS technology

Chiu¹,

Fang²,

Chou³

et al. 2007

Semicond. Sci. Technol.

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A new STI (shallow trench isolation) with automatic top corner rounding (ATCR) to improve 90 nm CMOS narrow width device performance has been studied in detail. Experimental results show that the ATCR mitigates the inverse narrow width effect, and increases the driving current (I dsat ) by 8% together in a unit process step, thus getting easy process control and cost down benefits, which cannot be achieved through conventional methods. Additionally, the ATCR attained a better trench depth uniformity, and thus a wider process window (20-50 s) than that of the conventional method. Furthermore, the technique does not degrade the gate oxide integrity and junction leakage current; thus the developed ATCR STI technique is more suitable for 90 nm and beyond narrow width CMOS technologies.

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CMOS shallow-trench-isolation to 50-nm channel widths

Cited by 13 publications

References 14 publications

A Silicon Nitride Based Shallow Trench Isolation with Side-Gate for CMOS Integration with MEMS Components for System-On-Chip Applications

A Silicon Nitride Based Shallow Trench Isolation with Side-Gate for CMOS Integration with MEMS Components for System-On-Chip Applications

A Robust Shallow Trench Isolation High Density Plasma Chemical Vapor Deposition Void Free Process for 0.13μm CMOS Technology

A novel STI etching technology to mitigate an inverse narrow width effect, and improve device performances for 90 nm node and beyond CMOS technology

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