A new STI (shallow trench isolation) with automatic top corner rounding (ATCR) to improve 90 nm CMOS narrow width device performance has been studied in detail. Experimental results show that the ATCR mitigates the inverse narrow width effect, and increases the driving current (I dsat ) by 8% together in a unit process step, thus getting easy process control and cost down benefits, which cannot be achieved through conventional methods. Additionally, the ATCR attained a better trench depth uniformity, and thus a wider process window (20-50 s) than that of the conventional method. Furthermore, the technique does not degrade the gate oxide integrity and junction leakage current; thus the developed ATCR STI technique is more suitable for 90 nm and beyond narrow width CMOS technologies.
In the paper, for the first time, the effects of shallow trench isolation (STI) stress enhanced boron diffusion on band-to-band (BTBT) leakage and Vccmin of a 65 nm node low-power SRAM are investigated in detail. High temperature oxidation in the STI process induces an elastic stress to enhance the diffusion of boron dopants, thus leading to a significant increase in BTBT on the STI edge sidewall. The enhanced boron diffusion is more serious for a shorter and/or narrower device, thus worsening the mismatch of the threshold voltage and Vccmin of the devices in a 65 nm node SRAM cell significantly.
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