A Unified Clock and Switched-Capacitor-Based Power Delivery Architecture for Variation Tolerance in Low-Voltage SoC Domains

Rahman, Fahim; Kim, Sung; John, Naveen; Kumar, Roshan; Li, Xi; Pamula, Rajesh; Bowman, Keith; Sathe, Visvesh

doi:10.1109/jssc.2018.2888866

Cited by 26 publications

(14 citation statements)

References 30 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In addition, power gating with frequency scaling [23] and body biasing (TEI-BB) [24], [25] have been presented, which exploit the TEI-benefit to further reduce the power consumption of ULV SoCs. Most recently, the efficacies of the TEI-VS and TEI-BB have been verified in fabricated chips in [26]- [28].…”

Section: B Tei-aware Low-power Techniquesmentioning

confidence: 99%

“…Similarly, the SoC in [26] uses a 65-nm process technology node and reports that it can operate with 9.2-MHz clock frequency at 0.48 V at 45 • C and at about 0.43 V at 100 • C. To emulate this SoC, a 65-nm technology-based FO4 inverter chain was designed and simulated. As a result, it was found that the minimum voltage can be dropped to 0.46 V at 45 • C and to 0.41 V at 100 • C while maintaining the same speed, indicating that SoC in [26] may not be able to fully utilize the TEI-benefit due to the wire delay. To sum up, compared to the existing SoCs, we can confirm that the TIP prototyping chip is excellent in making full use of the TEI-benefit.…”

Section: A Tei-benefit On Chipsmentioning

confidence: 99%

“…Due to the TEI phenomenon, ULV operating circuits have the opportunity to improve power consumption and performance, and a number of researchers have tried to exploit these ideas for dynamic power and thermal management methods [17]- [25]. Moreover, recent research has confirmed the effectiveness of these methods on fabricated System on Chips (SoCs) [26]- [28].…”

mentioning

confidence: 99%

See 2 more Smart Citations

Developing TEI-Aware Ultralow-Power SoC Platforms for IoT End Nodes

Han

Lee

et al. 2021

IEEE Internet Things J.

View full text Add to dashboard Cite

Ranging from circuit-level characterization to designing a platform architecture, developing a design automation tool, and fabricating a System on Chip (SoC), this article deals with the entire development process for ultralow-power (ULP) SoCs for Internet-of-Things (IoT) end nodes. More precisely, this article first focuses on the unique characteristics of the ULP circuits, the temperature effect inversion (TEI), i.e., the delay of the ULP circuits decreases with increasing temperature. Existing TEI-aware low-power (TEI-LP) techniques have incredible potential to further reduce the power consumption of conventional ULP SoCs, but there is a critical limitation to be widely adopted in real SoCs. To address this limitation and realize the ULP SoCs that can fully benefit from the TEI-LP techniques, this article proposes a new TEI-inspired SoC platform (TIP) architecture. On top of that, taking into account that the highly complex, time consuming, and labor-intensive development process of these ULP SoCs may hinder their widespread use for IoT end nodes, this article presents a new electronic design automation tool to accelerate ULP SoC development, RISC-V express (RVX). Finally, by using the RVX, this article introduces a TIP prototyping chip fabricated in 28-nm FD-SOI technology. This chip demonstrates that power savings of up to 35% can be achieved by lowering the supply voltage from 0.54 to 0.48 V at 25 • C and 0.44 V at 80 • C while continuing to operate at a target 50-MHz clock frequency.

show abstract

Section: B Tei-aware Low-power Techniquesmentioning

confidence: 99%

Section: A Tei-benefit On Chipsmentioning

confidence: 99%

mentioning

confidence: 99%

See 1 more Smart Citation

Developing TEI-Aware Ultralow-Power SoC Platforms for IoT End Nodes

Han

Lee

et al. 2021

IEEE Internet Things J.

View full text Add to dashboard Cite

show abstract

“…12(b). Then, this occurrence degrades the timing slack and may cause a failure of timing margin in the processor [62]- [64]. To avoid such issues, a voltage guardband should be introduced.…”

Section: A Typical Voltage and Frequency Regulators For Dvfsmentioning

confidence: 99%

Power Delivery Networks for Embedded Mobile SoCs: Architectural Advancements and Design Challenges

Akram

Hwang

2021

IEEE Access

View full text Add to dashboard Cite

Conventional power delivery networks (PDNs) and power management techniques using off-chip power converters with bulky passive components cannot meet the ever-evolving power delivery requirements of high-performance modern system-on-chips (SoCs). In SoCs, heterogeneous components, including multi-core processors and mixed-signals peripheral circuits, require state-of-the-art PDNs to provide high-quality power-on-demand with minimum latency, simultaneously achieving the small-factor, high conversion efficiency, and minimum current consumption. To satisfy these power delivery requirements, various PDNs have been developed over the past decades, such as the conventional architectures using off-chip power converters, architectures using in-package power converters and fully-integrated power converters, and heterogeneous architectures (off-chip power converters and on-chip regulators). This paper reviews these architectural advancements of the PDNs and their advantages and limitations, which leads us to discuss a heterogeneous PDN structure consisting of a highly efficient off-chip switching-mode power converter and multiple highly precise small linear regulators integrated on chip at point-of-load locations. The heterogeneous PDN has been proved one of the most suitable architectures to achieve high-quality finegrained on-chip power delivery and management in SoCs. This paper also discusses unified voltage and frequency regulators (UVFRs), which support dynamic-variation-aware dynamic voltage and frequency scaling (DVFS) for fine-grained power management in multi-core processors. Based on the UVFR, we propose a modified heterogeneous PDN using frequency-referenced digital low-dropout regulators (FR-DLDOs) for more efficient DVFS, eliminating the need for band-gap circuits to provide reference voltages. As an exemplary implementation of FR-DLDO for this PDN, we present an FR-DLDO with a transientboost control, which accelerates the transient response. The transient-boost control is activated dynamically only when an abrupt change happens out of the steady state. The implemented FR-DLDO fabricated in a 40-nm CMOS process outperforms other FR-DLDOs in the figure-of-merit and peak power efficiency while driving 40 mA of load current. INDEX TERMS Power delivery network (PDN); fine-grained power management; dynamic-voltage and frequency scaling (DVFS); dynamic-voltage scaling (DVS); low-dropout regulator (LDO); digital LDO; unified-voltage and frequency regulator (UVFR); frequency-referenced digital LDO (FR-DLDO); transientboost control.

show abstract

“…Internet of Things (IoT), mobile and medical application have urge the Very Large Scale Integrated circuites (VLSI) designer to build ultra-low power (ULP) circuits [1,2]. Since power consumption deceases quadratically with the drop of supply voltage, low-voltage technology is one of the important means to reduce the power consumption of digital circuits [3][4][5].…”

Section: Introductionmentioning

confidence: 99%

A Fast-Transient All-Digital LDO with Adaptive Clock Technique

Jia

Qiao

et al. 2019

Electronics

View full text Add to dashboard Cite

To get a better tradeoff between the transient performance and current efficiency of Digital Low-Dropout (DLDO) regulator, this paper proposes an all-digital Low-Dropout (LDO) regulator with adaptive clock technique. The sample clock is supplied by a proposed digital oscillator (DOSC) whose output frequency can be changed seamlessly. The frequency of sample clock and loop gain boost adaptively when the output voltage undershoot/overshoot is detected. Proposed DLDO integrates a ripple controller to eliminate steady-state supply ripple and reduce steady-state power. The proposed DLDO is simulated at Semiconductor Manufacturing International Corporation (SMIC) 55 nm with 5.03e-4 mm2 active area. The simulation results show that the operating voltage of proposed DLDO can be down to 0.5 V and the peak current efficiency is 99.99%. The measured voltage undershoot is 40 mV and transient response time is 500 ns with load step of 10 to 800 uA.

show abstract

A Unified Clock and Switched-Capacitor-Based Power Delivery Architecture for Variation Tolerance in Low-Voltage SoC Domains

Cited by 26 publications

References 30 publications

Developing TEI-Aware Ultralow-Power SoC Platforms for IoT End Nodes

Developing TEI-Aware Ultralow-Power SoC Platforms for IoT End Nodes

Power Delivery Networks for Embedded Mobile SoCs: Architectural Advancements and Design Challenges

A Fast-Transient All-Digital LDO with Adaptive Clock Technique

Contact Info

Product

Resources

About