A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier

Giefers, Heiner; Platzner, Marco

doi:10.1109/fpl.2010.52

Cited by 12 publications

(6 citation statements)

References 13 publications

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“…In this scenario, there are proposals whose implementation are based on a single FPGA [11][12][13][14], following the aim of our work, or on multi-FPGA [15][16][17], used to develop larger systems. One example is seen in [12], where the authors design a 2x3 virtual channel based NoC prototype on an Altera Stratix II FPGA.…”

Section: Related Workmentioning

confidence: 99%

Network-on-chip emulation framework for multimedia SoC development

2013

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Current tendencies of consumer electronics have envisaged multiprocessor System-on-Chip (SoC) as a promising solution for the high performance embedding systems, and, in this scenario, Network-on-chip communication paradigm is considered as a way to improve on-chip communication efficiency. In this paper, a NoC based SoC emulation framework is designed and implemented on a low-cost FPGA device.The objective of this work is the design and implementation of a prototyping platform with NoC topology, which provides a demonstrator for the implementation of multimedia applications. The emulation platform will allow evaluation, comparison, and verification of different aspects of a NoC design for SoCs intended for the execution of multimedia applications.The proposed emulation platform consists of different type of functional IP blocks (microprocessors, memory blocks, peripherals, additional blocks, etc.) interconnected through an interconnection infrastructure based on NoC. In order to provide a low-cost solution, the platform design is restricted to use a single FPGA, resulting in a low-scale SoC due to the limited resources available in the FPGA used. However, the proposed design may be scalable and replicate in large scale FPGA or multi-FPGA devices to increase emulation performance.In this work, a design flow, which integrates different commercial EDA tools, is presented, and integration process is discussed in detail due to problems experienced in this stage. The platform is fully implemented on a Xilinx Spartan-6 LX45T FPGA and special attention is given to verification and floorplanning stages. Finally, various multimedia applications with real-time requirements are executed on the NoC-based SoC platform. At this stage, the performance results are analyzed according to the type of application, as well as the number of processors required.

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Section: Related Workmentioning

confidence: 99%

Network-on-chip emulation framework for multimedia SoC development

2013

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“…Since the WECPAR model is theoretical, we do not go into the details of implementation. For some recent relevant possibilities, see, for example, [23], and for some optical alternatives, see [24], [25].…”

Section: Introductionmentioning

confidence: 99%

The Well-Connected Processor Array

Gordon

2014

IEEE Trans. Comput.

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A new theoretical model for reconfigurable processor arrays is introduced. Most of the models considered in the literature are similar to the reconfigurable mesh (RMESH), in which each processing element (PE) is connected to its four neighbors by reconfigurable buses. In the new model, called the "well-connected processor array" (WECPAR), every PE is connected to each neighbor by point-topoint lines, and it also controls the switching between those lines. is called the connectivity of the WECPAR. Any line entering the PE can either be connected to the PE itself, or it can be connected by the PE to another line, thus enabling complex switching configurations. This model is suitable for arrays in which the computation and memory areas of a PE are very much larger than a switch area. The concept of a burden placed on a PE by the lines connected to or passing through it is introduced. This is used to derive a lower bound of on the connectivity required by a WECPAR to embed any graph of degree with expansion ; for , this result is sharp. Various other issues are examined: graph embeddings, algorithms, broadcasting, routing, and self-simulation. A novel transportation-type routing method utilizes the connectivity for efficient routing. A sample algorithmic result is that an -point FFT can be done in logarithmic time on a WECPAR of PEs with a connectivity of .

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“…However, as has been discussed by [10] and [11], once the circuit is set up, circuit-switched NoCs on FPGA do have the advantages of guaranteed QoS and low data transmit latency. A circuit-switched network can also be used together with a packet-switched network to combine the advantages of both [12], [13]. A time-multiplexed NoC can take advantage of a pre-characterized communication pattern to achieve low resource utilization and reduced latency.…”

Section: Related Workmentioning

confidence: 99%

“…A switch arbiter is located in each output port and arbitrates between multiple requests from input ports. The static priority arbiter, such as the one used in [12], can save logic resources, but has a serious fairness problem which adversely impacts network throughput. We have therefore used a ripple arbiter [21] and a matrix arbiter [22] to provide roundrobin and least recently served schemes for switch arbitration.…”

Section: A Componentsmentioning

confidence: 99%

Generic Low-Latency NoC Router Architecture for FPGA Computing Systems

McCanny

Sezer

2011

2011 21st International Conference on Field Programmable Logic and Applications

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Abstract-A novel cost-effective and low-latency wormhole router for packet-switched NoC designs, tailored for FPGA, is presented. This has been designed to be scalable at system level to fully exploit the characteristics and constraints of FPGA based systems, rather than custom ASIC technology. A key feature is that it achieves a low packet propagation latency of only two cycles per hop including both router pipeline delay and link traversal delay -a significant enhancement over existing FPGA designs -whilst being very competitive in terms of performance and hardware complexity. It can also be configured in various network topologies including 1-D, 2-D, and 3-D. Detailed designspace exploration has been carried for a range of scaling parameters, with the results of various design trade-offs being presented and discussed. By taking advantage of abundant buildin reconfigurable logic and routing resources, we have been able to create a new scalable on-chip FPGA based router that exhibits high dimensionality and connectivity. The architecture proposed can be easily migrated across many FPGA families to provide flexible, robust and cost-effective NoC solutions suitable for the implementation of high-performance FPGA computing systems.

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A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier

Cited by 12 publications

References 13 publications

Network-on-chip emulation framework for multimedia SoC development

Network-on-chip emulation framework for multimedia SoC development

The Well-Connected Processor Array

Generic Low-Latency NoC Router Architecture for FPGA Computing Systems

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