Generic Low-Latency NoC Router Architecture for FPGA Computing Systems

Lu, Ye; McCanny, J.V.; Sezer, Sakir

doi:10.1109/fpl.2011.25

Cited by 25 publications

(3 citation statements)

References 23 publications

(29 reference statements)

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“…The incoming packets will be assigned to one of the middle memory buffers with two constraints: packets that are arriving at the same time must be assigned to different middle memories and an incoming packet cannot be assigned to a middle memory that already holds a packet with the same departure time which is tagged into each packet when they firstly arrive at the router. In [39], Lu et al propose a lowlatency wormhole router for packet-switched NoC designs. It achieves a low packet propagation latency of only two cycles per hop including both router pipeline delay and link traversal delay, which is a significant enhancement over existing FPGA designs.…”

Section: E Router Microarchitecture Designmentioning

confidence: 99%

Flexible and Efficient QoS Provisioning in AXI4-Based Network-on-Chip Architecture

Wang

2022

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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We propose a Network-on-Chip (NoC)-based whole system design, whose communication architecture is compatible with the AMBA AXI4 protocol and supports high-performance multiple Quality-of-Service (QoS) schemes. In our system, the network interface (NI) between the NoC and the master/slave node is proposed to make the NoC architecture independent from the AXI4 protocol via message format conversion between the AXI4 signal format and the packet format, offering high flexibility to the NoC design. Besides, a QoS inheritance mechanism is applied in the slave-side NI to support QoS during packets' round-trip transfer in the NoC. The NoC system contains Time Division Multiplexing (TDM) and Virtual Channel (VC) subnetworks to apply multiple QoS schemes to AXI4 signals with different QoS tags and the NI is responsible for signals distribution between two subnetworks. Besides, a traffic converter is proposed in each NI to balance the traffic between the two subnetworks when necessary. The experimental results show that our proposed architecture ensures a high-throughput and lowlatency NoC system. By applying traffic converter, the packet latency can be improved.

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Section: E Router Microarchitecture Designmentioning

confidence: 99%

Flexible and Efficient QoS Provisioning in AXI4-Based Network-on-Chip Architecture

Wang

2022

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…The study of Kumar et al [8] have focused on the design of area-efficient router framework based on FPGA for Network on chip, Once the completing of the design of channels, the crossbar is also designed and after the completing the process of design of crossbar and all four channels both designed are integrated with the making of the framework of a router. The work of Lu et al [9] have concentrated on the problem of delay in packet transmission and cost in routing, for solving this issue presented a Low-Latency NoC Router framework. The study of Monemi et al [10] has focused on the problem of a design of less time taking network on the chip with a low area overhead technique.…”

Section: Related Workmentioning

confidence: 99%

Fpga Implementation of Priority-Arbiter Based Router Design for Noc Systems

Nirmala¹,

Shylaja²

2019

IJARET

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An efficient Priority-Arbiter based Router is designed along with 2X2 and 3X3 mesh topology-based NOC architecture are designed. The Priority-Arbiter based Router design includes Input registers, Priority arbiter, and XY-Routing algorithm. The Priority-Arbiter based Router and NOC 2X2 and 3X3 Router designs are synthesized and implemented using Xilinx ISE Tool and simulated using Modelsim6.5f. The implementation is done by Artix-7 FPGA device, and the physically debugging of the NOC 2X2 Router design is verified using Chipscope pro tool. The performance results are analyzed in terms of the Area (Slices, LUT's), Timing period, and Maximum operating frequency. The comparison of the Priority-Arbiter based Router is made concerning previous similar architecture with improvements.

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“…A low-latency wormhole router for packet-switched NoC designs, for Field Programmable Gate Array (FPGA), is presented in [7]. This has been designed to be scalable at system level to fully exploit the characteristics and constraints of FPGA based systems, rather than custom ASIC technology.…”

Section: Related Workmentioning

confidence: 99%

Design of Efficient Router with Low Power and Low Latency for Network on Chip

Deivakani¹,

Shanthi²

2016

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The NoC consists of processing element (PE), network interface (NI) and router. This paper proposes a hybrid scheme for Netwok of Chip (NoC), which aims at obtaining low latency and low power consumption by concerning wired and wireless links between routers. The main objective of this paper is to reduce the latency and power consumption of the network on chip architecture using wireless link between routers. In this paper, the power consumption is reduced by designing a low power router and latency is reduced by implementing a on-chip wireless communication as express links for transferring data from one subnet routers to another subnet routers. The average packet latency and normalized power consumption of proposed hybrid NoC router are analyzed for synthetic traffic loads as shuffle traffic, bitcomp traffic, transpose traffic and bitrev traffic. The proposed hybrid NoC router reduces the normalized power over the wired NoC by 12.18% in consumer traffic, 12.80% in AutoIndust traffic and 12.5% in MPEG2 traffic. The performance is also analyzed with real time traffic environments using Network simulator 2 tool.

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Generic Low-Latency NoC Router Architecture for FPGA Computing Systems

Cited by 25 publications

References 23 publications

Flexible and Efficient QoS Provisioning in AXI4-Based Network-on-Chip Architecture

Flexible and Efficient QoS Provisioning in AXI4-Based Network-on-Chip Architecture

Fpga Implementation of Priority-Arbiter Based Router Design for Noc Systems

Design of Efficient Router with Low Power and Low Latency for Network on Chip

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