A three-step decomposition method for the evolutionary design of sequential logic circuits

Abstract

Evolvable hardware (EHW) refers to an automatic circuit design approach, which employs evolutionary algorithms (EAs) to generate the configurations of the programmable devices. The scalability is one of the main obstacles preventing EHW from being applied to real-world applications. Several techniques have been proposed to overcome the scalability problem. One of them is to decompose the whole circuit into several small evolvable sub-circuits. However, current techniques for scalability are mainly used to evolve combinational logic circuits. In this paper, in order to decompose a sequential logic circuit, the state decomposition, output decomposition and input decomposition are united as a threestep decomposition method (3SD). A novel extrinsic EHW system, namely 3SD-ES, which combines the 3SD method with the (l, k) ES (evolution strategy), is proposed, and is used for the evolutionary designing of larger sequential logic circuits. The proposed extrinsic EHW system is tested extensively on sequential logic circuits taken from the Microelectronics Center of North Carolina (MCNC) benchmark library. The results demonstrate that 3SD-ES has much better performance in terms of scalability. It enables the evolutionary designing of larger sequential circuits than have ever been evolved before.

Designing the combinational logic circuits with hybrid of Generalized Disjunction Decomposition and Evolutionary Repair

“…Evolutionary design of logic circuits [2][3][4] is a research topic in the Evolvable Hardware [5] field, which adopts Evolutionary Algorithms (EAs) [6,7] to generate the logic circuits automatically. Compared with traditional logic circuit design methods, the evolutionary design method needs less domain knowledge and could generate creative structures.…”

Improvement of Optimization in Design of Synchronous Sequential Circuits by Using Evolvable Hardware

“…However, relatively few efforts have been done to evolving sequential logic circuits [1]. The works have been done in the field of sequential circuits are presented in Table 1.…”

Evolutionary design of complex digital circuits based on hierarchical module composition and predominant component prevention

“…We have employed an evolution strategy adapted from the method [4] for evolution of each individual in each layer. This evolution process consists of five steps: (i) generate an initial population of GPinds and Cells, and then initialise the Rank List of VPL; (ii) evaluate the fitness of every Cells for each output line and evaluate the usage of GPinds in the Cells; (iii) if the fitness condition of all output lines is satisfied or the maximum generation is reached, terminate the program; (iv) otherwise, the next generation should be started, and GPL collects GPinds used by Cells and then regenerates GPinds from its usage; (v) generate offspring Cells from the elites of each output line and go back to step (ii).…”