A TCAD approach to robust ESD design in oxide-confined VCSELs

Developments at Finisar AOC

“…2,5 In a single mode VCSEL, however, with their much smaller apertures, two micrometers from an edge may well be past the center of the aperture, so we would predict that damage would occur near the center. In addition, the higher series resistance means that a greater fraction of the total power dissipation during any ESD event is due to I²R heating, which occurs in the mirrors, not in the junction plane.…”

Reliability investigation and failure analysis of 25Gb/s 850 nm oxide-confined VCSELs

“…From the XS-TEM results corresponding to the defects, it can be found that a large number of defects appear at the oxide tip and propagate downward to the DBRs and QW regions. The generation mechanisms of these different failure features are closely related to the shock waveform of the ESD mode and the specific device structure [16][17][18].…”