A SystemC refinement methodology for embedded software

Chevalier, J. G.; Nanclas, M. de; Filion, L.; Benny, Olivier; Rondonneau, Mathieu; Bois, Guy; Aboulhamid, E.M.

doi:10.1109/mdt.2006.27

Cited by 18 publications

(10 citation statements)

References 9 publications

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“…SPACE [15] is a research project between the École Polytechnique de Montréal and the Université de Montréal. SPACE is based on the idea of extending the SystemC language to fully encompass software and operating system layers, and defining specific refinement abstraction layers to allow abstract system models to be refined down into accurate HW-SW models that may include multiple heterogeneous or homogeneous processors.…”

Section: Related Workmentioning

confidence: 99%

Multi-Processor SoC-Based Design Methodologies Using Configurable and Extensible Processors

Martín¹

2007

J Sign Process Syst Sign Image Video Technol

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The growing interest in multiprocessor system-on-chip (MPSoC) design, or 'multicore' processors, has resulted in some confusion between the various types of multiprocessor architectures and their suitability in different application spaces. In particular, there are clear differences between the general-purpose, symmetric multiprocessor (SMP) approaches, and the application-specific, asymmetric multiprocessor (AMP) architectures. Configurable and extensible processors are especially suited for the AMP approach, yet their flexibility means that new design methodologies and tools must be developed to allow effective utilisation of multiple instructionset processors in a complex design. Configurable and extensible processors are especially well suited for dataintensive computational tasks, such as are found in many signal and image processing applications, including audio, video, and wireless and wired networking. A design methodology for such applications must pay careful attention to the right programming models, and dataflow styles of processing seem a natural fit to the application space. In this paper, we describe a design methodology, flow and tools for MPSoC design using configurable and extensible processors that is especially interesting for data-intensive dataflow style applications. Some of the issues involved in this design approach are used to highlight opportunities for ongoing research.

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Section: Related Workmentioning

confidence: 99%

Multi-Processor SoC-Based Design Methodologies Using Configurable and Extensible Processors

Martín¹

2007

J Sign Process Syst Sign Image Video Technol

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“…This represents a strong limitation for SystemC-based co-design approaches, considered that embedded software now routinely accounts for 80% of embedded system development costs [17]. Some works [3,18,19,20,21] have been proposed to overcome the previous limitation by integrating RTOS capability in the C++/SystemC design flow, to improve the support to SW refinement. In [3] the authors present SoCOS, a system-level design environment for modeling and simulating embedded system.…”

Section: Introductionmentioning

confidence: 99%

“…This prevents an efficient evaluation of different HW/SW configurations. To facilitate HW/SW partitioning, a different approach is presented in [21]. The authors propose a SystemC refinement methodology that focuses on using SW abstraction levels to enhance high-level embedded SW modeling support.…”

Section: Introductionmentioning

confidence: 99%

A Smooth Refinement Flow for Co-designing HW and SW Threads

Destro¹,

Fummi²,

Pravadelli³

2007

2007 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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“…One ultimate goal is to allow for early embedded SW development based on a virtual prototype of the HW platform. Much work has been done in embedded SW generation from a transaction-level description [1,2,5,9,12,15]. Typical to these approaches is that the SW developers are obliged to use a dedicated TLM API in order to access the functionality of HW IP.…”

Section: Introductionmentioning

confidence: 99%

“…1 shows a typical transaction-level model of a simple system-on-chip (SoC) with a HW core and a SW subsystem. In such models, communication between concurrent SW processes is modeled by using an RTOS API [2,5,10,15]. This is indicated by the dotted arrows between the SW processes P1 and P2.…”

Section: Introductionmentioning

confidence: 99%

Embedded software development on top of transaction-level models

Klingauf

Günzel

Schröder

2007

Proceedings of the 5th IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis

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Early embedded SW development with transaction-level models has been broadly promoted to improve SoC design productivity. But the proposed APIs only provide low-level read/write operations via a TLM interconnect. SW developers have to implement platform-specific communication procedures and handshake protocols to access HW functions, which requires a deep understanding of both the HW interfaces and the TLM fabric used. In this paper, we propose our concept of hardware procedure calls (HPC) with which HW services are provided to SW processes as remote methods on top of transaction-level communication. To this end, a lightweight HPC protocol is presented, and we propose a method to generate the infrastructure for HPC communication from a straightforward input description. Our experiments show that with HPC, embedded SW development is considerably made easier, and that also the effort to create the transaction-level model itself is reduced.

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A SystemC refinement methodology for embedded software

Cited by 18 publications

References 9 publications

Multi-Processor SoC-Based Design Methodologies Using Configurable and Extensible Processors

Multi-Processor SoC-Based Design Methodologies Using Configurable and Extensible Processors

A Smooth Refinement Flow for Co-designing HW and SW Threads

Embedded software development on top of transaction-level models

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