A Systematic Approach to Qualification of 90 nm Low-K Flip-Chip Packaging

Vissa, U.; Butel, N.; Rowatt, John David; Thielen, C.; McCann, David; Collins, J.V.

doi:10.1109/ectc.2006.1645618

Cited by 6 publications

(3 citation statements)

References 6 publications

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“…PEDL showed the much less Von-Mises stress, shear stress, and warpage, as well as die corner stress. In failure and reliability issues in Cu/low-packaging, the edge or corner Cu/low-stack delamination is one of the major failure mode [4]. So this is quite promising result to prevent Cu/low- …”

Section: B Mechanical Simulation On the Bump With Polymer Encapsulatmentioning

confidence: 98%

150-$\mu{\rm m}$ Pitch Cu/Low-${\rm k}$ Flip Chip Packaging With Polymer Encapsulated Dicing Line (PEDL) and Cu Column Interconnects

Yoon

Thew

Lim

et al. 2008

IEEE Trans. Adv. Packag.

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This paper focuses on the packaging process and assembly and interlayer dielectrics (ILD) structural stability including mechanical simulation with polymer-encapsulation and redistribution process for 150-m pitch Pb-free flip chip packaging of low-k/Cu interconnects. Chemical vapor deposition (CVD) type low-test vehicles with four Cu layers were fabricated using Cu dual damascene process. Polymer encapsulation and metal redistribution (RDL) technology were applied using wafer integration technology to minimize the stress from the solder bump pad to low-ILD. This polymer encapsulated dicing line (PEDL) was introduced and the result of investigation discussed. Finite element method (FEM) mechanical simulations are performed for RDL approach, normal direct bumping, and PEDL. According to the results with shear loading, RDL approach showed less stress than that of direct bumping at the solder joint. Simulation indicated the die corner stress is reduced significantly on chip with PEDL as compared to that without PEDL. For copper postinterconnects, cost-effective and thick photoresist process was developed and optimized for electro Cu plating and solder was deposited on the top of Cu post. Bump shear test was carried out to evaluate the bump quality and failures were analyzed. After flip chip assembly with Cu/low-devices having via-chain and daisychain interconnects, various JEDEC standard reliability tests were carried out and failure analysis was performed.Index Terms-CU/low-packaging, CU post, flip chip packaging, high lead solder, solder joint reliability.

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Section: B Mechanical Simulation On the Bump With Polymer Encapsulatmentioning

confidence: 98%

150-$\mu{\rm m}$ Pitch Cu/Low-${\rm k}$ Flip Chip Packaging With Polymer Encapsulated Dicing Line (PEDL) and Cu Column Interconnects

Yoon

Thew

Lim

et al. 2008

IEEE Trans. Adv. Packag.

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“…Results of a Pbfree qualification with 90nm device were presented last year for a 4-2-4 build-up laminate package (3). It is common knowledge in the industry that in addition to Pb-free bumping and organic package requirements, low-k dielectrics are required for high-performance devices in the 90nm and tighter device ground rules (1,2). We present results of a Pbfree CPI technology qualification of 200um pitch bumps on a 65nm device with low-k wiring on a thin-core 2-2-2 laminate package.…”

Section: Introductionmentioning

confidence: 96%

Qualification of Low-k 65nm Technology Die with Pb-free Bumps on a 2-2-2 Laminate Package (PBGA) with Pb-free Assembly Processes

Ray

Muncy

McLaughlin

et al. 2007

2007 Proceedings 57th Electronic Components and Technology Conference

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Flip-chip carriers have become the preferred solution for high-performance ASIC and microprocessor devices. Typically these are packaged in organic or ceramic Ball Grid Array (BGA) connections. Recently, there has been a significant focus on Pb-free packages to meet European Union mandated RoHS guidelines by 2006, with exemptions allowed for server and other networking hardware (1,2).Towards this goal, IBM has developed and qualified Pb-free and Pb-reduced packages that cover advanced semiconductor technologies such as 130nm and 90nm ground rules. In addition, for device performance reasons, the BEOL wiring layers on the high-performance 90nm or smaller ground rule devices also require low-k dielectric materials. Finally, due to tighter wiring ground rules and faster device performance requirements, the build-up laminate packages require thincore (400 um) and advanced wiring pitch in the build-up layers. IBM has partnered with Amkor Technology to qualify both 130nm and 90nm devices with Amkor developed Pb-free bumps using large die and build-up laminates, the details of which were presented at the 56th ECTC (3). The Sn-Ag Pbfree plated bumps were fabricated by Amkor on 300mm wafers with photosensitive polyimide (PSPI) passivation. Details of Amkor-Unitive plated Pb-free bump technology are discussed in Reference 4. The die size used was 14.7mm and the laminate qualified was 42.5mm with a structure of 4-2-4. We have extended the Pb-free low-k device technology to evaluate two additional elements: 65nm ground rules with enhanced low-k wiring layers on the die, and a 2-2-2 structure with thin core. The work reported here has been done with IBM silicon fabricated in the 300mm facility in East Fishkill, New York. Pb-free bumping and BA was carried out by Amkor.In this paper, we will summarize the Sn/Ag Pb-free plated bumps that have been qualified for low-k 65nm technology on thin-core build-up laminates. The bump pitch is 200um, and the laminate size is 42.5mm. One of the key issues addressed in this qualification was whether Pb-free bumps along with assembly to build-up laminates with thin-core result in enough stress to cause any low-k related fails such as delamination or cracks in the low-k wiring layers. In IBM this is carried out with special wiring and via-chains on the testdie that are monitored after assembly to package, and through reliability testing -perimeter lines, and delamination sensors, serpentines, and via-chains on the test-die that are tested for continuity and isolation of individual nets. These structures survive wafer-level stressing, and fails in modules are due to additional stress or damage induced by the bond and assembly processes. This is known as Chip-Package Interaction or CPI evaluation.Typical reliability stressing was carried out for Pb-free 65nm die for CPI and 2-2-2 PBGA package qualification described in the paper. The 200um pitch Pb-free bumps on a 216 sq.mm die successfully completed these reliability stresses for both CPI and package without any CPI net, bump or laminate wirin...

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“…For cost consideration, organics substrate has been employed instead of the more expensive ceramic substrate [6,7]. The tradeoff is CTE mismatch between the silicon chip and substrate resulted in larger thermal strain in solder joint.…”

Section: Introductionmentioning

confidence: 99%

Impact of packaging design on reliability of large die Cu/low-κ (BD) interconnect

Chai

Zhang

et al. 2008

2008 58th Electronic Components and Technology Conference

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This paper presents the study on the effect of low κ stacked layer, chip pad design structures, and shift pad design of a large die size Cu/low κ (BD ™ ) chip for improving assembly and reliability performance on organic buildup substrate FCBGA (FlipChip Ball Grid Array). Bump shear characterization has been performed on the integrity of different stacked layer and pad structure, supported by bump shear modeling analysis. Initial reliability testing was performed on assembled package to identify the best choice of design and finally implemented on the reliability test vehicle for verification. In addition, a potential chip crack problem due to excessive warpage in FCBGA with large die assembly is examined and a simple failure criterion is proposed.

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A Systematic Approach to Qualification of 90 nm Low-K Flip-Chip Packaging

Cited by 6 publications

References 6 publications

150-$\mu{\rm m}$ Pitch Cu/Low-${\rm k}$ Flip Chip Packaging With Polymer Encapsulated Dicing Line (PEDL) and Cu Column Interconnects

150-$\mu{\rm m}$ Pitch Cu/Low-${\rm k}$ Flip Chip Packaging With Polymer Encapsulated Dicing Line (PEDL) and Cu Column Interconnects

Qualification of Low-k 65nm Technology Die with Pb-free Bumps on a 2-2-2 Laminate Package (PBGA) with Pb-free Assembly Processes

Impact of packaging design on reliability of large die Cu/low-κ (BD) interconnect

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A Systematic Approach to Qualification of 90 nm Low-K Flip-Chip Packaging

Cited by 6 publications

References 6 publications

150-$\mu{\rm m}$ Pitch Cu/Low-${\rm k}$ Flip Chip Packaging With Polymer Encapsulated Dicing Line (PEDL) and Cu Column Interconnects

150-$\mu{\rm m}$ Pitch Cu/Low-${\rm k}$ Flip Chip Packaging With Polymer Encapsulated Dicing Line (PEDL) and Cu Column Interconnects

Qualification of Low-k 65nm Technology Die with Pb-free Bumps on a 2-2-2 Laminate Package (PBGA) with Pb-free Assembly Processes

Impact of packaging design on reliability of large die Cu/low-&#x03BA; (BD) interconnect

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Product

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Impact of packaging design on reliability of large die Cu/low-κ (BD) interconnect