Qualification of Low-k 65nm Technology Die with Pb-free Bumps on a 2-2-2 Laminate Package (PBGA) with Pb-free Assembly Processes

Abstract

Flip-chip carriers have become the preferred solution for high-performance ASIC and microprocessor devices. Typically these are packaged in organic or ceramic Ball Grid Array (BGA) connections. Recently, there has been a significant focus on Pb-free packages to meet European Union mandated RoHS guidelines by 2006, with exemptions allowed for server and other networking hardware (1,2).Towards this goal, IBM has developed and qualified Pb-free and Pb-reduced packages that cover advanced semiconductor technologies such as 130nm and 90nm ground rules. In addition, for device performance reasons, the BEOL wiring layers on the high-performance 90nm or smaller ground rule devices also require low-k dielectric materials. Finally, due to tighter wiring ground rules and faster device performance requirements, the build-up laminate packages require thincore (400 um) and advanced wiring pitch in the build-up layers. IBM has partnered with Amkor Technology to qualify both 130nm and 90nm devices with Amkor developed Pb-free bumps using large die and build-up laminates, the details of which were presented at the 56th ECTC (3). The Sn-Ag Pbfree plated bumps were fabricated by Amkor on 300mm wafers with photosensitive polyimide (PSPI) passivation. Details of Amkor-Unitive plated Pb-free bump technology are discussed in Reference 4. The die size used was 14.7mm and the laminate qualified was 42.5mm with a structure of 4-2-4. We have extended the Pb-free low-k device technology to evaluate two additional elements: 65nm ground rules with enhanced low-k wiring layers on the die, and a 2-2-2 structure with thin core. The work reported here has been done with IBM silicon fabricated in the 300mm facility in East Fishkill, New York. Pb-free bumping and BA was carried out by Amkor.In this paper, we will summarize the Sn/Ag Pb-free plated bumps that have been qualified for low-k 65nm technology on thin-core build-up laminates. The bump pitch is 200um, and the laminate size is 42.5mm. One of the key issues addressed in this qualification was whether Pb-free bumps along with assembly to build-up laminates with thin-core result in enough stress to cause any low-k related fails such as delamination or cracks in the low-k wiring layers. In IBM this is carried out with special wiring and via-chains on the testdie that are monitored after assembly to package, and through reliability testing -perimeter lines, and delamination sensors, serpentines, and via-chains on the test-die that are tested for continuity and isolation of individual nets. These structures survive wafer-level stressing, and fails in modules are due to additional stress or damage induced by the bond and assembly processes. This is known as Chip-Package Interaction or CPI evaluation.Typical reliability stressing was carried out for Pb-free 65nm die for CPI and 2-2-2 PBGA package qualification described in the paper. The 200um pitch Pb-free bumps on a 216 sq.mm die successfully completed these reliability stresses for both CPI and package without any CPI net, bump or laminate wirin...