Impact of packaging design on reliability of large die Cu/low-&amp;#x03BA; (BD) interconnect

Chai, Tai Chong; Zhang, Xiaowu; Li, H.Y.; Sekhar, Vasarla Nagendra; Hnin, Wai Yin; Thew, Meei Ling; Navas, O.K.; Lau, John H.; Murthy, Ramana; Balakumar, S.; Tan, Y.M.; Cheng, Chia-Ming; Liew, Siao Li; Chi, Dongzhi; Zhu, W.H.

doi:10.1109/ectc.2008.4549948

Cited by 13 publications

(3 citation statements)

References 5 publications

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“…The CE principle of reducing packaging dismissal forces it to become circular by extending its lifecycle through reuse or remanufacturing and maintaining its reliability along successive cycles [62]. The "design for manufacturing and assembly" (DfMA), "design for reliability" (DfR), and "design for sustainability" (DfS) support the DfX approach for packaging circularity [53].…”

Section: Dfx Approaches Relevant For Sustainable Packaging Productsmentioning

confidence: 99%

Circularity Micro-Indicators for Plastic Packaging and Their Relation to Circular Economy Principles and Design Tools

Matos,

Martins,

Simoes

2024

Sustainability

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Plastic packaging, in the form of films, brought several advantages to the commercialization of products given its lightness and durability. It provided better ergonomics, ease of transport, increased shelf life, and easy handling and use. Despite that, plastic packaging is facing enormous sustainability concerns associated with the traditional practice of linear economy, combined with commonplace irresponsible handling by citizens since it is almost exclusively designed for single-use and its end-of-life (EOL) management is not planned for. To mitigate that, the circularity of plastic packaging must be more clearly studied and evaluated through approaches such as micro-level circular economy (CE) indicators. This paper focuses on the selection of relevant CE micro-indicators specifically for the plastic packaging sector among the plethora of indicators available. Relations are also established between CE micro-indicators and CE guiding principles, as well as the most prevalent Design for X (DfX) approaches, providing new insights into how these different aspects of sustainability can be linked together. Results show three micro-level indicators as the most relevant for circularity calculation in packaging, namely those termed ‘MCI’, ‘VRE’, and ‘CEIP’, because their methodology and approach address most of the CE guiding principles and DfX approaches relevant for the packaging sector. Finally, guidelines and good practices to promote circularity adoption in the plastic packaging sector are highlighted. This work can guide companies aiming to adopt CE micro-indicators in their practical implementation, overcoming the significant knowledge barrier that currently exists.

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Section: Dfx Approaches Relevant For Sustainable Packaging Productsmentioning

confidence: 99%

Circularity Micro-Indicators for Plastic Packaging and Their Relation to Circular Economy Principles and Design Tools

Matos,

Martins,

Simoes

2024

Sustainability

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“…The semiconductor industry has spent tremendous effort to develop and integrate low-k and ultra-low-k (ULK) materials into the backend of the line (BEoL) stack for the clear benefits of faster performance and lower power consumption. However, low dielectric constants directly correlate to weaker chemical bonding in the materials, which inherently reduces mechanical strength [6]. Such reliability issues are receiving increasing attention from IC manufacturing designers [7,8].…”

Section: Introductionmentioning

confidence: 99%

An Investigation on the Most Likely Failure Locations in the BEoL Stack of a 20 nm Chip Due to Chip Package Interaction with the Use of Novel Semi-Elliptical Cracks

Li,

Shi,

Tay

et al. 2023

Micromachines

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The era of 20 nm integrated circuits has arrived. There exist abundant heterogeneous micro/nano structures, with thicknesses ranging from hundreds of nanometers to sub-microns in the IC back end of the line stack, which put stringent demands on the reliability of the device. In this paper, the reliability issues of a 20 nm chip due to chip–package interaction during the reflow process is studied. A representative volume element of the detailed complex BEoL structure has been analyzed to obtain mechanical properties of the BEoL stack by adopting a sub-model analysis. For the first time, semi-elliptical cracks were used in conjunction with J-integral techniques to analyze the failure caused by Chip-to-Package Interaction for a 20 nm chip. The Energy Release Rate(ERR)for cracks at various interfaces and locations in the BEoL stack were calculated to predict the most likely mode and location of failure. We found that the ERR of interfacial cracks at the bottom surface of the interconnects are, on average, more than double those at the sidewalls, which are in turn more than double the number of cracks in the low-k inter-layer dielectric. A total of 500 cycles of thermal shock were conducted, which verified the predictions of the finite element simulations.

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“…The need for faster, lower cost and smaller devices with higher performance and power requirements has required changes in the chip fabrication and assembly processes that can further exacerbate these reliability issues from node-to-node. For example the introduction of the mechanically weaker low-k and ultra-low-k (ULK) dielectrics for lower capacitance, improved device speed and better signal integrity is one such change that has been done recently that drastically impacted the structural integrity of the assembled chip during reliability testing [1]. Other structural and material changes, such as increasing die size, finer wiring and C4 (controlled collapse chip connection) solder interconnect pitch, more stressful lead-free solder bumps, and the use of organic laminates to support the high performance and lower cost requirements of the newer Si technologies has led to both weaker and more highly stressed parts that are susceptible to early mechanical failures due to solder fatigue, delamination and cracks in the underfill and in the weaker BEOL interlayer dielectrics (ILD) [2][3][4][5].…”

Section: Introductionmentioning

confidence: 99%

C4 EM and CPI Reliability Benefits and Process Challenges of FBEOL Integration Changes Implemented in Lead-free C4 Products

Misra

Wassick

Melville

et al. 2015

International Symposium on Microelectronics

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The introduction of low-k & ultra-low-k dielectrics, lead-free (Pb-free) solder interconnects or C4's, and organic flip-chip laminates for integrated circuits have led to some major reliability challenges for the semiconductor industry. These include C4 electromigration (EM) and mechanical failures induced with-in the Si chip due to chip-package interactions (CPI). In 32nm technology, certain novel design changes were evaluated in the last Cu wiring level and the Far Back End of Line levels (FBEOL) to strategically re-distribute the current more uniformly through the Pb-free C4 bumps and therefore improve the C4 EM capabilities of the technology. FBEOL process integration changes, such as increasing the thickness of the hard dielectric (SiNx & SiOx) and reducing the final via diameter, were also evaluated for reducing the mechanical stresses in the weaker BEOL levels and mitigating potential risks for mechanical failures within the Si chip. The supporting white-bump, C4 EM and electrical/mechanical modeling data that demonstrates the benefits of the design and integration changes will be discussed in detail in the paper. Some of the key processing and integration challenges observed due to the design and process updates and the corresponding mitigation steps taken will also be discussed.

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Impact of packaging design on reliability of large die Cu/low-κ (BD) interconnect

Cited by 13 publications

References 5 publications

Circularity Micro-Indicators for Plastic Packaging and Their Relation to Circular Economy Principles and Design Tools

Circularity Micro-Indicators for Plastic Packaging and Their Relation to Circular Economy Principles and Design Tools

An Investigation on the Most Likely Failure Locations in the BEoL Stack of a 20 nm Chip Due to Chip Package Interaction with the Use of Novel Semi-Elliptical Cracks

C4 EM and CPI Reliability Benefits and Process Challenges of FBEOL Integration Changes Implemented in Lead-free C4 Products

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