Understanding and managing both chip-to-package interaction (CPI) and solder bump electromigration (EM) in new designs is becoming an increasing challenge for flip chip plastic ball grid array (FCPBGA) packaging. Requirements for state-of-the-art device technologies drive smaller features, higher power and RoHS compliance (Pb-free product). It will be shown that the optimal attributes for Pb-free solder bump EM performance often are diametrically opposed to the design parameters that improve CPI robustness in structures comprised of low-k dielectric materials.
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