A system-level stochastic circuit generator for FPGA architecture evaluation

Mark, Cindy; Shui, A.; Wilton, Steven J. E.

doi:10.1109/fpt.2008.4762362

Cited by 7 publications

(2 citation statements)

References 10 publications

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“…We chose to use synthetic circuits because the circuits in the traditional MCNC benchmark suite are too small for this study. The synthetic benchmarks mimic modern system-level designs and were generated us- ing the tool published in [16]. We use the entire MCNC suite of circuits to form the IP library needed by the circuit generation tool.…”

Section: Cad and Benchmarksmentioning

confidence: 99%

Towards scalable FPGA CAD through architecture

Chin

Wilton

2011

Proceedings of the 19th ACM/SIGDA International Symposium on Field Programmable Gate Arrays

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Long FPGA CAD runtime has emerged as a limitation to the future scaling of FPGA densities. Already, compile times on the order of a day are common, and the situation will only get worse as FPGAs get larger. Without a concerted effort to reduce compile times, further scaling of FPGAs will eventually become impractical.Previous works have presented fast CAD tools that tradeoff quality of result for compile time. In this paper, we take a different but complementary approach. We show that the architecture of the FPGA itself can be designed to be amenable to fast-compile. If not done carefully, this can lead to lower-quality mapping results, so a careful tradeoff between area, delay, power, and compile run-time is essential. We investigate the extent to which run-time can be reduced by employing high-capacity logic blocks. We extend previous studies on logic block architectures by quantifying the area, delay and CAD runtime trade-offs for large capacity blocks, and also investigate some multi-level logic block architectures. In addition, we present an analytically derived equation to guide the design of logic block I/O requirements.

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Section: Cad and Benchmarksmentioning

confidence: 99%

Towards scalable FPGA CAD through architecture

Chin

Wilton

2011

Proceedings of the 19th ACM/SIGDA International Symposium on Field Programmable Gate Arrays

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“…The synthetic benchmarks (synth 1 through synth 8) are generated using a tool published by Mark et al [32]. The open source benchmarks that are used in this experiment are distributed with Odin-II [33].…”

Section: A Experimental Methodologymentioning

confidence: 99%

Identifying and placing heterogeneously-sized cluster groupings based on FPGA placement data

Gharibian¹,

Shannon²,

Jamieson

2014

2014 24th International Conference on Field Programmable Logic and Applications (FPL)

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Field Programmable Gate Arrays (FPGAs) CAD flow run-time has increased due to the rapid growth in size of designs and FPGAs. Researchers are trying to find new ways to improve compilation time without degrading design performance. In this paper, we present a novel approach that identifies tightly grouped FPGA logic blocks and then uses this information during circuit placement. Our approach is an orthogonal optimization applicable in incremental design and physical optimization, and reduces placement run-time. Specifically, we present a new algorithm that analyzes designs post-placement to extract mediumgrained super-clusters that consist of two to seventeen clusters, which we call "gems". We modified VPR's simulated annealing placement algorithm to place our mixture of gems and clusters. Our new "Singularity Annealing" algorithm first crushes each cluster grouping into a "singularity" (treated as a single cluster). Then, the Singularity Annealer is run over this condensed circuit to obtain an initial placement, followed by an expansion of the singularities. Finally, we run a second low-temperature annealing phase on the entire expanded circuit. Our results show that our system reduces placement run-time on average by 17% while maintains the designs critical path delay, and increases designs channel width, and wirelength by 2% and 6.3%, respectively. We have also presented a test case to show the re-usability of gems in an incremental design example.

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Exploring FPGA technology mapping for fracturable LUT minimization

Dickin

Shannon

2011

2011 International Conference on Field-Programmable Technology

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A system-level stochastic circuit generator for FPGA architecture evaluation

Cited by 7 publications

References 10 publications

Towards scalable FPGA CAD through architecture

Towards scalable FPGA CAD through architecture

Identifying and placing heterogeneously-sized cluster groupings based on FPGA placement data

Exploring FPGA technology mapping for fracturable LUT minimization

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