A System-Level Cosynthesis Framework for Power Delivery and On-Chip Data Networks in Application-Specific 3-D ICs

Models of computation for NoC mapping: Timing and energy saving awareness

“…Normally, static energy is responsible for the smallest part of the energy consumption; however, for deep-submicron technologies, the designer cannot neglect the leakage current effect. ST Energy and time reduction Mesh CTG (CqPqd) [11]; [9] ST Energy, area and time reduction Clos, torus, mesh Core graph (Cq) [12] ST Energy saving and bandwidth reservation Mesh APCG (Cq) [13] ST Energy and time reduction Mesh CWM, CDM (Cq, Cqd) [14] ST Energy and time reduction Mesh CDM, CDCM (Cqd, CqdPq) [13] ST Energy and latency reduction Mesh, torus, fat-tree ACP (Cqo) [15] ST Energy saving Mesh ECWM (Cq) [16]; [17]; [18] ST Energy and area reduction Mesh, torus Core graph (Cq) [19] ST Hops minimization and thermal balance Mesh APCG (Cq) [20] ST Energy and area reduction, QoS Ad hoc Multigraph (Cq) [21] ST Energy saving Mesh Task graph (Pqd) [22] DY Energy and time minimization Mesh ACG (CqPq) [23] ST Energy saving Mesh WCTG (Cq) [24] DY Energy, channel occupation, latency reduction Mesh CDCM (CqdPq) [25] ST Energy reduction Regular tile MACTG (CqPqd) [26] DY Energy and congestion reduction Mesh CTG (CqPqd) [27] ST Energy saving Regular tile ACG (CqdPq) [28] ST Latency minimization and throughput increase Mesh Task graph (Cq) [29] ST Energy and latency reduction Mesh ACG (CqPq) [30] ST Energy saving Mesh Task graph (CqPqd) [31] DY Load balance and comm. overhead reduction Mesh ATG (CqoPqo) [32] DY Hotspot avoidance, uniform energy consumption Mesh CTG (Pqd) [33] ST Hops minimization Mesh TFG (Cqo) [34] DY Energy and time saving Mesh ATG (Cqd) [35] ST Energy and latency reduction Ad hoc Core graph (Cq) [36] DY, ST Time saving and real-time constraints fulfilling Abstract model KPN (CqoPqo) [37] DY, ST Energy efficiency Mesh ACG (Cq) [38] DY Time and energy saving Mesh DAG (Cqd) [39] DY, ST Energy saving, load balancing Mesh TCG (Cq)…”

A Software Framework for Rapid Application-Specific Hybrid Photonic Network-on-Chip Synthesis

“…Efforts on regular NoC topology synthesis primarily focus on mapping uniform sized cores and their communication flows on regular mesh topologies to optimize energy and performance [29][30][31][32][33][34]. For instance, Ascia et al [30] use a genetic algorithm approach to map cores and their communication flows on a die to minimize communication power in a mesh NoC.…”

“…Kapadia et al [32] propose a heuristic approach to enable a voltage island-aware low-power mapping of cores and communication routes on a regular mesh NoC. Kapadia et al [34] also proposed a 3-D NoC-PDN cosynthesis framework to minimize communication power in a regular NoC while also reducing worst-case IR-drops in the power delivery network (PDN). Other efforts focus on application specific synthesis of irregular NoCs [35][36][37][38][39][40].…”