A Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion

Ojima, Naoki; Nakura, Toru; Iizuka, Tetsuya; Asada, Kunihiro

doi:10.1109/vlsi-soc.2018.8644879

Cited by 7 publications

(8 citation statements)

References 4 publications

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“…With the aim of speeding up the design time and to drastically reduce the area usage of analog building blocks, researchers have recently focused on optimizing and refining novel layout strategies, searching for a way to automate the design flow of analog blocks by using some features, such as the automatic place and route strategies for standard-cell based circuits, typically adopted in the digital design flow to implement fully-synthesizable comparators [12]- [15], ADCs [16]- [19], DACs [20], LDOs [21]- [23] and OTAs [2], [24]- [27].…”

Section: Introductionmentioning

confidence: 99%

A Novel Differential to Single-Ended Converter for Ultra-Low-Voltage Inverter-Based OTAs

2022

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For the design of inverter-based OTAs with differential input and single-ended output, the differential to single-ended (D2S) converter is a key building block. In fact, the performance of the D2S strongly affects the overall common-mode rejection ratio (CMRR) and input common-mode range (ICMR) of the whole OTA. In recent literature, inverter-based OTAs rely on a D2S topology based on an inverter driving another inverter with the input and output tight together which behaves as a "diode" connected device to implement a voltage gain approximately equal to −1. However, since this approach is based on the matching of the inverters, the performance of this D2S results sensitive to PVT variations if the bias point of the inverters is not properly stabilized. In this paper we present a novel topology of inverterbased D2S converter, exploiting an auxiliary, standard-cell-based, error amplifier and a local feedback loop. The proposed D2S, compared to the conventional one, exhibits higher CMRR, improved ICMR and better robustness with respect to PVT variations. We present also an ULV, standard-cell-based OTA, which exploits the proposed D2S converter and shows excellent performance figures of merit with low area footprint.

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Section: Introductionmentioning

confidence: 99%

A Novel Differential to Single-Ended Converter for Ultra-Low-Voltage Inverter-Based OTAs

2022

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“…In these solutions, generally, analog circuits are described in RTL netlists and automatically laid out in digital P&R flows. Recent works have succeeded in time-to-digital converters (TDCs) [1]- [3], phase-locked loops (PLLs) [4]- [11], low-dropout (LDO) regulators [12]- [14], and analogto-digital converters (ADCs) [15]- [24]. As the interface between the real world and digital signal processing, ADCs are widely needed in sensor and radio frequency systems.…”

Section: Introductionmentioning

confidence: 99%

An All-Standard-Cell-Based Synthesizable SAR ADC With Nonlinearity-Compensated RDAC

Ojima

et al. 2021

IEEE Trans. VLSI Syst.

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We propose an all-standard-cell-based synthesizable successive-approximation-register analog-to-digital converter (SAR ADC) which is automatically placed and routed (P&R) using a commercial digital implementation tool. For higher feasibility and wider input range, a differential architecture is proposed with an inverter-based resistive digital-to-analog converter (RDAC) and a four-input comparator. MOSFET gate capacitance is employed for the sampling capacitor. To mitigate its capacitance variation due to input voltage and the leakage between gate and diffusion, we leave the diffusion of the standard cell floating and only use the capacitance between gate and bulk. Two prototypes have been designed in 65-nm bulk CMOS. Prototype I has been fabricated and achieves 10 MS/s, 14.3 mW, and 28.1-dB SNDR in a 6-bit architecture. The performance is improved in Prototype II by proposing a lookup table (LUT)-compensating transistor-configurable inverter-based RDAC and an OR-AND-Inverter (OAI)-based comparator and by employing a thick-oxide diffusion-floating decoupling cell for the sampling capacitor. The default LUT is created during the design phase by a script-controlled automatic simulation routine. The power consumption is significantly reduced as well through improved timing control. Layout-parasitic-extraction (LPE) simulations of Prototype II suggest 35.7-and 47.2-dB SNDRs in 6-and 8-bit versions, respectively. The power consumptions are reduced to 0.91 and 2.52 mW, respectively.

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“…Since the comparator offset increases the error of ADC, there may be a deviation in the regulation. In [17][18][19], a time-to-digital converter (TDC) is employed to replace ADC. To convert the output voltage to digital codes, the TDC alters the buffer-gate's propagation delay by changing the power supply of the buffer-gate.…”

Section: Introductionmentioning

confidence: 99%

A Fast Transient Response Digital LDO with a TDC-Based Signal Converter

Zhang¹,

Wan²,

Geng³

et al. 2020

Electronics

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The digital low drop-out regulator (LDO) has been used widely in digital circuits for its low supply voltage characteristics. However, as the traditional digital LDOs regulate the output voltage code at a rate of 1 bit per clock cycle, the transient response speed is limited. This paper presents a digital LDO to improve transient response speed with a multi-bit conversion technique. The proposed technology uses a voltage sensor and a time-to-digital converter to convert the output voltage to digital codes. Based on a 65-nm CMOS process, the proposed DLDO reduces the settling time from 147.8 ns to 25.2 ns on average and the response speed is improved by about six times.

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A Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion

Cited by 7 publications

References 4 publications

A Novel Differential to Single-Ended Converter for Ultra-Low-Voltage Inverter-Based OTAs

A Novel Differential to Single-Ended Converter for Ultra-Low-Voltage Inverter-Based OTAs

An All-Standard-Cell-Based Synthesizable SAR ADC With Nonlinearity-Compensated RDAC

A Fast Transient Response Digital LDO with a TDC-Based Signal Converter

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