The digital low drop-out regulator (LDO) has been used widely in digital circuits for its low supply voltage characteristics. However, as the traditional digital LDOs regulate the output voltage code at a rate of 1 bit per clock cycle, the transient response speed is limited. This paper presents a digital LDO to improve transient response speed with a multi-bit conversion technique. The proposed technology uses a voltage sensor and a time-to-digital converter to convert the output voltage to digital codes. Based on a 65-nm CMOS process, the proposed DLDO reduces the settling time from 147.8 ns to 25.2 ns on average and the response speed is improved by about six times.
Affected by solar radiation, atmospheric windows, radiation aberrations, and other air and sky environmental factors, remote sensing images usually contain a large amount of noise and suffer from problems such as non-uniform image feature density. These problems bring great difficulties to the segmentation of high-precision remote sensing image. To improve the segmentation effect of remote sensing images, this study adopted an improved metaheuristic algorithm to optimize the parameter settings of pulse-coupled neural networks (PCNNs). Using the Taguchi method, the optimal parallelism scheme of the algorithm was effectively tailored for a specific target problem. The blindness in the design of the algorithm parallel structure was effectively avoided. The superiority of the customized parallel SCA based on the Taguchi method (TPSCA) was demonstrated in tests with different types of benchmark functions. In this study, simulations were performed using IKONOS, GeoEye-1, and WorldView-2 satellite remote sensing images. The results showed that the accuracy of the proposed remote sensing image segmentation model was significantly improved.
Digital low drop-out regulator (D-LDO) with fast settling time and superior transient response is gaining increasing attention to make up for the deficiency of analog LDO. However, as the traditional digital LDOs regulate the output voltage code at a rate of 1 bit per clock cycle, the transient response speed is limited. In this paper, a multi-bit conversion technique is proposed to improve the transient response speed. The multi-bit conversion technique is achieved by an error detector with adaptive regulation of proportion and integration parameters in the digital controller before pass devices. Besides, a voltage sensor and a time-to-digital converter are employed to convert the output voltage to digital codes. Implemented in a 180-nm CMOS process, the proposed D-LDO features under 36/33 mV of undershoot/overshoot at VOUT = 0.95 V as the load current steps up with 40 mA/1 ns on a 0.5 nF load capacitor. The simulated response time is 0.18-ns, the figure-of-merit of speed FOM1 is 0.65 ps and FOM2 achieves 0.068 pF.
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