A synthesizable datapath-oriented embedded FPGA fabric

Wilton, Steven J. E.; Ho, Chun Hok; Leong, Philip H. W.; Luk, Wayne; Quinton, B.R.

doi:10.1145/1216919.1216924

Cited by 18 publications

(7 citation statements)

References 18 publications

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“…The ASIC synthesis tool reports that the area of a single-precision coarse-grained unit is 433 780 m . We further assume 15% overhead after place and route the design based on our experience [12]. The area values are normalized against the feature size (0.13 m).…”

Section: Resultsmentioning

confidence: 99%

“…In earlier work, we described the VEB technique for modeling heterogeneous blocks using commercial tools [10], domain-specific hybrid FPGAs [11], and a word-based synthesizable FPGA architecture [12]. This paper provides a unified view of these studies, describes the proposed FPGA architecture in greater detail, presents improved results through the use of a higher performance commercial floating-point core, introduces the mapping process for the FPFPGA, discusses the requirement of a hardware compiler dedicated to such FPFPGA device, and includes two new synthetic benchmark circuits in the study, one of which is twice the size of the largest circuit studied previously.…”

Section: A Related Workmentioning

confidence: 99%

“…Each wordblock contains identical bitblocks, and is similar to our earlier published design [12]. A bitblock contains two 4-input LUTs and a reconfigurable output register.…”

Section: B Architecturementioning

confidence: 99%

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Floating-Point FPGA: Architecture and Modeling

Leong

et al. 2009

IEEE Trans. VLSI Syst.

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Abstract-This paper presents an architecture for a reconfigurable device that is specifically optimized for floating-point applications. Fine-grained units are used for implementing control logic and bit-oriented operations, while parameterized and reconfigurable word-based coarse-grained units incorporating word-oriented lookup tables and floating-point operations are used to implement datapaths. In order to facilitate comparison with existing FPGA devices, the virtual embedded block scheme is proposed to model embedded blocks using existing field-programmable gate array (FPGA) tools. This methodology involves adopting existing FPGA resources to model the size, position, and delay of the embedded elements. The standard design flow offered by FPGA and computer-aided design vendors is then applied and static timing analysis can be used to estimate the performance of the FPGA with the embedded blocks. On selected floating-point benchmark circuits, our results indicate that the proposed architecture can achieve four times improvement in speed and 25 times reduction in area compared with a traditional FPGA device.

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Section: Resultsmentioning

confidence: 99%

Section: A Related Workmentioning

confidence: 99%

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Floating-Point FPGA: Architecture and Modeling

Leong

et al. 2009

IEEE Trans. VLSI Syst.

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“…As described in [18], each WB contains identical bitblocks, each consisting of two 4-input LUTs and a reconfigurable register. The value of depends on the bit-width of the FPU.…”

Section: B Coarse-grained Blockmentioning

confidence: 99%

“…This technique can enumerate all possible common subgraphs; we only include subgraphs with two or more nodes. graph2, 3,4,6,9,10,23,24,25,27,28,30,31,32,33,34,35,39,40,41 occur in two benchmark circuits; graph5, 8,13,22,36 occur in three benchmark circuits; graph14, 16,17,20,38 are common in four benchmark circuits; graph1, 7,18,21,26,37 are common in five benchmark circuits; graph11,19,29 are used in six benchmark circuits; and graph12,15 are used in seven benchmark circuits. Since our standard cell library is for a 0.13-m process and our fine-grained fabric modelled in VPH uses a 0.15-m process, normalized area (area/feature size squared) is used.…”

Section: B Fpu Architecture Optimizationmentioning

confidence: 99%

Optimizing Floating Point Units in Hybrid FPGAs

Smith

Luk

et al. 2012

IEEE Trans. VLSI Syst.

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Abstract-This paper introduces a methodology to optimize coarse-grained floating point units (FPUs) in a hybrid field-programmable gate array (FPGA), where the FPU consists of a number of interconnected floating point adders/subtracters (FAs), multipliers (FMs), and wordblocks (WBs). The wordblocks include registers and lookup tables (LUTs) which can implement fixed point operations efficiently. We employ common subgraph extraction to determine the best mix of blocks within an FPU and study the area, speed and utilization tradeoff over a set of floating point benchmark circuits. We then explore the system impact of FPU density and flexibility in terms of area, speed, and routing resources. Finally, we derive an optimized coarse-grained FPU by considering both architectural and system-level issues. This proposed methodology can be used to evaluate a variety of FPU architecture optimizations. The results for the selected FPU architecture optimization show that although high density FPUs are slower, they have the advantages of improved area, area-delay product, and throughput.Index Terms-Common subgraph extraction, field-programmable gate array (FPGA), floating point (FP).

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Customisation of on-chip network interconnects and experiments in field-programmable gate arrays

Hur

Stefanov

Wong

et al. 2012

IET Comput. Digit. Tech.

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Conventional rigid and generalpurpose on-chip networks occupy significant logic and wire resources in fieldprogrammable gate arrays (FPGAs). To reduce the area cost, the authors present a topology customisation technique, using which on-demand network interconnects are systematically established in reconfigurable hardware. First, the authors present a design of a customised crossbar switch, where physical topologies are identical to logical topologies for a given application. A multiprocessor system combined with the presented custom crossbar has been designed with the ESPAM design environment and prototyped in the FPGA device. Experiments with practical applications show that the custom crossbar occupies significantly less area, maintains higher performance and reduces the power consumption, when compared with the general-purpose crossbars. In addition, the authors present that configuration performance and cost can be improved by reducing the functional area cost in FPGAs. Second, a customisation technique for the circuit-switched network-on-chip (NoC) is presented, where only necessary half-duplex interconnects are established for a given application mapping. The presented customised NoC is implemented in FPGA and results indicate that the area is reduced by 66%, when compared with the general-purpose networks.

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A synthesizable datapath-oriented embedded FPGA fabric

Cited by 18 publications

References 18 publications

Floating-Point FPGA: Architecture and Modeling

Floating-Point FPGA: Architecture and Modeling

Optimizing Floating Point Units in Hybrid FPGAs

Customisation of on-chip network interconnects and experiments in field-programmable gate arrays

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