A Survey of Phase Change Memory Systems

Xia, Fei; Jiang, Dongxiang; Xiong, Jin; Sun, Ninghui

doi:10.1007/s11390-015-1509-2

Cited by 45 publications

(18 citation statements)

References 85 publications

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“…We also noticed an intensification of research in the NVM area in the last 6 years. This is probably due to the growing popularity of NAND Flash Solid-State Disks (SSDs) and the growing maturity and promising specifications of new NVM technologies, especially the Phase-Change RAM (PCRAM) [137] and Spin-Transfer Torque RAM (STT-RAM) [93].…”

Section: B Applying the Search Stringmentioning

confidence: 99%

Non-Volatile Memory File Systems: A Survey

et al. 2019

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For decades, computer architectures have treated memory and storage as separate entities. Nowadays, we watch the emergence of new memory technologies that promise to significantly change the landscape of memory systems. Byte-addressable non-volatile memory (NVM) technologies are expected to offer access latency close to that of dynamic random access memory and capacity suited for storage, resulting in storage-class memory. However, they also present some limitations, such as limited endurance and asymmetric read and write latency. Furthermore, adjusting the current hardware and software architectures to embrace these new memories in all their potential is proving to be a challenge in itself. In this paper, recent studies are analyzed to map the state-of-the-art of NVM file systems research. To achieve this goal, over 100 studies related to NVM systems were selected, analyzed, and categorized according to their topics and contributions. From the information extracted from these papers, we derive the main concerns and challenges currently being studied and discussed in the academia and industry, as well as the trends and solutions being proposed to address them.

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Section: B Applying the Search Stringmentioning

confidence: 99%

Non-Volatile Memory File Systems: A Survey

et al. 2019

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“…The rate at which the material is cooled down determines the stored bit; slow cooling stores bit "1" and fast cooling stores bit "0" on the cell. To later read a PCM cell, the state of the material is detected by applying a low voltage to it [33]. The resistive characteristic of PCM cells allows them to retain their data for a long time with no need for periodic refreshes.…”

Section: Background 21 Phase Change Memory (Pcm)mentioning

confidence: 99%

Writeback-Aware LLC Management for PCM-Based Main Memory Systems

Pourshirazi

Beigi

Zhu

et al. 2019

ACM Trans. Des. Autom. Electron. Syst.

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With the increase in the number of data-intensive applications on today's workloads, DRAM-based main memories are struggling to satisfy the growing data demand capacity. Phase Change Memory (PCM) is a type of non-volatile memory technology that has been explored as a promising alternative for DRAM-based main memories due to its better scalability and lower leakage energy. Despite its many advantages, PCM also has shortcomings such as long write latency, high write energy consumption, and limited write endurance, which are all related to the write operations. In this article, we propose a novel writeback-aware Last Level Cache (LLC) management scheme named WALL to reduce the number of LLC writebacks and consequently improve performance, energy efficiency, and lifetime of a PCM-based main memory system. First, we investigate the writeback behavior of LLC sets and show that writebacks are not uniformly distributed among sets; some sets observe much higher writeback rates than others. We then propose a writeback-aware set-balancing mechanism, which employs the underutilized LLC sets with few writebacks as an auxiliary storage for the evicted dirty lines from sets with frequent writebacks. We also propose a simple and effective writeback-aware replacement policy to avoid the eviction of the dirty blocks that are highly reused after being evicted from the cache. Our experimental results show that WALL achieves an average of 30.9% reduction in the total number of LLC writebacks, compared to the baseline scheme, which uses the LRU replacement policy. As a result, WALL can reduce the memory energy consumption by 23.1% and enhance PCM lifetime by 1.29×, on average, on an 8-core system with a 4GB PCM main memory, running memory-intensive applications. CCS Concepts: • Computer systems organization → Processors and memory architectures; • Hardware → Emerging technologies;

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“…Other techniques to increase PCM lifetime by evenly distributing writes over the whole memory (known as wear-leveling) [35] as well as write reduction techniques utilizing row shifting and page swapping are also available and can be found in recent review paper such as [12] . Approaches such as in [36,37] address the write endurance problem on the software level by optimizing the application software/system software to reduce write operation.…”

Section: Related Workmentioning

confidence: 99%

“…The limited write endurance of PCM hinders its widespread usage in computers and embedded systems [12] . Therefore, enhancing PCM lifetime is of great importance especially if is to replace DRAMs in the future.…”

Section: Introductionmentioning

confidence: 99%