Non-Volatile Memory File Systems: A Survey

Puglia, Gianlucca Oliveira; Zorzo, Avelino F.; Rose, César A. F. De; Perez, Taciano

doi:10.1109/access.2019.2899463

Cited by 15 publications

(11 citation statements)

References 121 publications

(139 reference statements)

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“…From an operating system perspective, we assume it uses a PM-aware file system, which is designed specifically for PM. 22 A PM-aware file system provides direct access to PM, removing the block I/O layer, bypassing the page cache, and eliminating other steps rendered unnecessary by PM, as data can be directly addressed by the processor at byte granularity. Examples of such file systems are BPFS, 23 PRAMFS, 24 PMFS, 25 Ext4/DAX, 26 SCMFS, 27 NOVA, 28 and M1FS.…”

Section: Proposed Designmentioning

confidence: 99%

Orthogonal persistence in nonvolatile memory architectures: A persistent heap design and its implementation for a Java Virtual Machine

Perez

Neves

Medaglia³

et al. 2019

Softw Pract Exp

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Summary Current computer systems separate main memory from storage, and programming languages typically reflect this distinction using different representations for data in memory and storage. However, moving data back and forth between these different layers and representations compromise both programming and execution efficiency. To remedy this, the concept of orthogonal persistence (OP) was proposed in the early 1980s advocating that, from a programmer's standpoint, there should be no differences in the way that short‐term and long‐term data are manipulated. However, at that time, the underlying implementations still had to cope with the complexity of moving data across memory and storage. Today, recent nonvolatile memory (NVM) technologies, such as resistive RAM and phase‐change memory, allow main memory and storage to be collapsed into a single layer of persistent memory, opening the way for more efficient programming abstractions for handling persistence. In this work, we revisit OP concepts in the context of NVM architectures and propose a persistent heap design for languages with automatic memory management. We demonstrate how it can significantly increase programmer and execution efficiency, removing the impedance mismatch of crossing semantic boundaries. To validate and demonstrate the presented concepts, we present JaphaVM, an implementation of the proposed design based on JamVM, an open‐source Java Virtual Machine. Our results show that JaphaVM, in most cases, executes the same operations between one and two orders of magnitude faster than regular database‐based and file‐based implementations, while requiring significantly less lines of code.

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Section: Proposed Designmentioning

confidence: 99%

Orthogonal persistence in nonvolatile memory architectures: A persistent heap design and its implementation for a Java Virtual Machine

Perez

Neves

Medaglia³

et al. 2019

Softw Pract Exp

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“…PCM, however, suffers from limited endurance, poor write performance, and considerable write power [22][23][24][25][26], which makes it an ineffective candidate for NVB-Buffers. Moreover, existing NVM candidates such as Flash, Ferroelectric RAM (FeRAM), 3D-Xpoint, and Resistive RAM (ReRAM) either suffer from high write latency (3D-XPoint, ReRAM, and Flash) or limited lifetime (3D-XPoint, Flash, and FeRAM) [17,[27][28][29][30]. Fig.…”

Section: Introductionmentioning

confidence: 99%

“…Among these candidates, Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) technology meets the PJA requirements arXiv:2202.13409v1 [cs.AR] 27 Feb 2022 Fig. 1: Overview of existing NVMs with respect to ideal PJA requirements [17,[27][28][29][30][31][32][33][34][35][36][37][38][39][40] of non-volatility [17], high endurance [31], and DRAMcomparable performance [17], as well as high density and negligible leakage current [32]. Therefore, compared to the other PJA candidates, STT-MRAM is considered as one of the most promising technologies for NVB-Buffers [14,17,[28][29][30][31].…”

Section: Introductionmentioning

confidence: 99%

CoPA: Cold Page Awakening to Overcome Retention Failures in STT-MRAM Based I/O Buffers

Hadizadeh¹,

Cheshmikhani²,

Rahmanpour³

et al. 2022

IEEE Trans. Parallel Distrib. Syst.

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Performance and reliability are two prominent factors in the design of data storage systems. To achieve higher performance, recently storage system designers use Dynamic RAM (DRAM)-based buffers. The volatility of DRAM brings up the possibility of data loss and data inconsistency. Thus, a part of the main storage is conventionally used as the journal area to be able of recovering unflushed data pages in the case of power failure. Moreover, periodically flushing buffered data pages to the main storage is a common mechanism to preserve a high level of reliability. This scheme, however, leads to a considerable increase in storage write traffic, which adversely affects the performance. To address this shortcoming, recent studies offer a small N on−V olatile M emory (NVM) as the P ersistent Journal Area (PJA) along with DRAM as an efficient approach to overcome DRAM vulnerability against power failure while effectively reducing storage write traffic. This approach, named N V M −Backed Buf f er (NVB-Buffer), features from advantages of NVMs and addresses DRAM shortcomings. In this paper, we employ the most promising technologies for PJA among the emerging technologies, which is Spin−T ransf er T orque M agnetic Random Access M emory (STT-MRAM) to meet the requirements of efficient PJA by providing high endurance, non-volatility, and DRAM-like latency. Despite these advantages, STT-MRAM faces major reliability challenges, i.e. Retention Failure, Read Disturbance, and Write Failure, which have not been addressed in previously suggested NVB-Buffers. In this paper, we first demonstrate that the retention failure is the dominant source of errors in NVB-Buffers as it suffers from long and unpredictable page idle intervals (i.e., the time interval between two consecutive accesses to a PJA page). Then, we propose a novel NVB-Buffer management scheme, named, Cold P age Awakening (CoPA), which predictably reduces the idle time of PJA pages. To this aim, CoPA employs Distant Ref reshing to periodically overwrite the vulnerable PJA page contents by opportunistically using their replica in DRAM-based buffer. We compare CoPA with the state-of-the-art schemes over several well-known storage workloads based on physical journaling. Our evaluations show that CoPA significantly reduces the maximum page idle time, which leads to three orders of magnitude lower failure rate with negligible performance degradation (1.1%) and memory overhead (1.2%).

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“…Therefore, our background is restricted to this scope. As such, our presentation does not cover the use of DCPMM and other PM technologies to store crash-consistent persistent data structures, which is a complementary research avenue that has been surveyed in other papers [3], [41].…”

Section: Introductionmentioning

confidence: 99%

Dynamic Page Placement on Real Persistent Memory Systems

Marques¹,

Kuzmin²,

Barreto³

et al. 2021

Preprint

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As persistent memory (PM) technologies emerge, hybrid memory architectures combining DRAM with PM bring the potential to provide a tiered, byte-addressable main memory of unprecedented capacity. Nearly a decade after the first proposals for these hybrid architectures, the real technology has finally reached commercial availability with Intel Optane™ DC Persistent Memory (DCPMM). This raises the challenge of designing systems that realize this potential in practice, namely through effective approaches that dynamically decide at which memory tier should pages be placed.In this paper, we are the first, to our knowledge, to systematically analyze tiered page placement on real DCPMM-based systems. To this end, we start by revisiting the assumptions of state-of-the-art proposals, and confronting them with the idiosyncrasies of today's off-the-shelf DCPMM-equipped architectures. This empirical study reveals that some of the key design choices in the literature rely on important assumptions that are not verified in present-day DRAM-DCPMM memory architectures.Based on the lessons from this study, we design and implement HyPlacer, a tool for tiered page placement in off-the-shelf Linux-based systems equipped with DRAM+DCPMM. In contrast to previous proposals, HyPlacer follows an approach guided by two main practicality principles: 1) it is tailored to the performance idiosyncrasies of off-theshelf DRAM+DCPMM systems; and 2) it can be seamlessly integrated into Linux with minimal kernel-mode components, while ensuring extensibility to other HMAs and other data placement policies. Our experimental evaluation of HyPlacer shows that it outperforms both solutions proposed in past literature and placement options that are currently available in off-the-shelf DCPMM-equipped Linux systems, reaching an improvement of up to 11x when compared to the default memory policy in Linux.

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Non-Volatile Memory File Systems: A Survey

Cited by 15 publications

References 121 publications

Orthogonal persistence in nonvolatile memory architectures: A persistent heap design and its implementation for a Java Virtual Machine

Orthogonal persistence in nonvolatile memory architectures: A persistent heap design and its implementation for a Java Virtual Machine

CoPA: Cold Page Awakening to Overcome Retention Failures in STT-MRAM Based I/O Buffers

Dynamic Page Placement on Real Persistent Memory Systems

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