A Survey of Homogeneous and Heterogeneous System Architectures in High Performance Computing

Gao, Yuxiang; Zhang, Peng

doi:10.1109/smartcloud.2016.36

Cited by 26 publications

(13 citation statements)

References 24 publications

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“…The heterogeneous many-core architecture is widely used in the fields of highperformance computing and scientific computing [13,32]. Because it requires a large number of cores [5], which can provide a high degree of parallelism and a high computing speed, reducing the energy consumption of many-core architectures has become a major challenge.…”

Section: Introductionmentioning

confidence: 99%

“…Because it requires a large number of cores [5], which can provide a high degree of parallelism and a high computing speed, reducing the energy consumption of many-core architectures has become a major challenge. To reduce the energy consumption, accelerator cores with local memories are provided in this architecture [13]. However, this means that two different kinds of memories are utilized in this architecture, i.e., off-chip memory and on-chip memory, which results in a more complex storage system, a profound challenge of which is determining how to handle the data transfer between off-chip memory and on-chip memory.…”

Section: Introductionmentioning

confidence: 99%

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Compiler-directed scratchpad memory data transfer optimization for multithreaded applications on a heterogeneous many-core architecture

Tao¹,

Pang²,

Jiang³

et al. 2021

J Supercomput

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The heterogeneous many-core architecture plays an important role in the fields of high-performance computing and scientific computing. It uses accelerator cores with on-chip memories to improve performance and reduce energy consumption. Scratchpad memory (SPM) is a kind of fast on-chip memory with lower energy consumption compared with a hardware cache. However, data transfer between SPM and off-chip memory can be managed only by a programmer or compiler. In this paper, we propose a compiler-directed multithreaded SPM data transfer model (MSDTM) to optimize the process of data transfer in a heterogeneous many-core architecture. We use compile-time analysis to classify data accesses, check dependences and determine the allocation of data transfer operations. We further present the data transfer performance model to derive the optimal granularity of data transfer and select the most profitable data transfer strategy. We implement the proposed MSDTM on the GCC complier and evaluate it on Sunway TaihuLight with selected test cases from benchmarks and scientific computing applications. The experimental result shows that the proposed MSDTM improves the application execution time by 5.49$$\times$$ × and achieves an energy saving of 5.16$$\times$$ × on average.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Compiler-directed scratchpad memory data transfer optimization for multithreaded applications on a heterogeneous many-core architecture

Tao¹,

Pang²,

Jiang³

et al. 2021

J Supercomput

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“…Going deeper into the characteristics of modern heterogeneous systems [1], [2], researchers have found many factors that contribute to making the task of applications development to be more complicated. Some of the factors are issues related to the integration of dissimilar processors on one chip, such as contention for shared resources, e.g., highest-level cache, interconnection network, limited bandwidth of the PCI-E bus, and limited memory of accelerators [3].…”

Section: Introductionmentioning

confidence: 99%

A Proposed Data Partitioning Approach on Heterogeneous HPC Platforms: Data Locality Perspective

Al-Hashimi

Basuhail

2021

IEEE Access

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We propose a new data partitioning approach to improve the performance of heterogeneous parallel applications in modern high-performance computing (HPC) systems. Existing approaches do not consider an important aspect that has a critical impact on the performance of parallel applications: the method of assigning partitions to each processor so as to minimize the communication cost and hence minimize data movement, which dominates energy and performance cost. Such an aspect for managing data locality is important for a large range of applications. Therefore, to achieve efficient data partitioning, we propose a method for distribution considering this aspect. Our algorithm seeks to minimize execution time by using two models. The first is a fine-grained computational model of heterogeneous processors, which is sufficiently adequate and accurate to guarantee efficient partitioning results that maximize utilization. The second is a communication model of heterogeneous processors to minimize data motion and hide communication overheads. The correctness of our algorithm was analyzed and validated. The complexity of our algorithm is approximately of order ( × + × ), where is (where steps is the step size between data points in the computational model of each processor), and is the number of heterogeneous processors. The experiments were performed on AZIZ supercomputer using two types of applications: an application with no dependency between its partitions, i.e., matrix multiplication, and another one with high dependency between its partitions, i.e., the Jacobi method. The results show the efficiency of our algorithm in improving performance.

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“…Each piece of these devices is designed based on the predefined tasks of a specific board. Since these devices are designed to focus on specific sort of applications, sometimes heterogeneous devices consist different set and types of cores [1][2][3][4][5][6], and that add more challenges in order to measure performance or find the best suitable simulation technique. High performance computing (HPC) community started the journey of these accelerators when they used Graphics Processing Units (GPUs) as accelerators for general purpose computations [7] and that what derived the term of General Purpose Computing on GPUs (GPGPU) [8].…”

Section: Introductionmentioning

confidence: 99%

“…Measuring the performance of these verity of accelerators is a critical task, since they are diverse and been designed for completely different purposes, customizable devices [1] [2]. Accurately scale of performance requires extensive programs writing just to achieve primary implementation.…”

Section: Introductionmentioning

confidence: 99%

A study of recent contributions on performance and simulation techniques for accelerator devices

Ajam

Agyeman

2017

2017 4th International Conference on Electrical and Electronic Engineering (ICEEE)

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Abstract-High performance computing platform is moving from homogeneous individual unites to heterogeneous systems. Where each unit is a combination of homogeneous cores and accelerator devices. Accelerator such as GPUs, FPGAs, DSPs, these devices usually designed for the specific and intensive type of computing tasks. The presence of these devices have created fresh and attractive development platforms for developers and designers, brand new performance analysis frameworks and optimization tools. This is the cutting edge in the performance of some accelerator devices like GPUs and Intel's Xeon Phi. We outline some of the existing heterogeneous systems and their development frameworks. The core of this study is a review of performance modeling of these devices. In this paper, we address the emerging issues that affect the performance of these devices and associated techniques employed for simulation and evaluation.

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A Survey of Homogeneous and Heterogeneous System Architectures in High Performance Computing

Cited by 26 publications

References 24 publications

Compiler-directed scratchpad memory data transfer optimization for multithreaded applications on a heterogeneous many-core architecture

Compiler-directed scratchpad memory data transfer optimization for multithreaded applications on a heterogeneous many-core architecture

A Proposed Data Partitioning Approach on Heterogeneous HPC Platforms: Data Locality Perspective

A study of recent contributions on performance and simulation techniques for accelerator devices

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