A Survey of Fault-Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays

Abstract

Nano-crossbar arrays have emerged as a promising and viable technology to improve computing performance of electronic circuits beyond the limits of current CMOS. Arrays offer both structural efficiency with reconfiguration and prospective capability of integration with different technologies. However, certain problems need to be addressed and the most important one is the prevailing occurrence of faults. Considering fault rate projections as high as 20% that is much higher than those of CMOS, it is fair to expect sophisticated fault tolerance methods. The focus of this survey paper is the assessment and evaluation of these methods and related algorithms applied in logic mapping and configuration processes. As a start, we concisely explain reconfigurable nano-crossbar arrays with their fault characteristics and models. Following that, we demonstrate configuration techniques of the arrays in the presence of permanent faults and elaborate on two main fault tolerance methodologies, namely defect-unaware and defect-aware approaches, with a short review on advantages and disadvantages. For both methodologies, we present detailed experimental results of related algorithms regarding their strengths and weaknesses with a comprehensive yield, success rate, and runtime analysis. Next, we overview fault tolerance approaches for transient faults. As a conclusion, we overview the proposed algorithms with future directions and upcoming challenges.

Yield analysis of nano-crossbar arrays for uniform and clustered defect distributions

“…This approach also produced low yield results as well. Another important tendency worth mentioning, majority of logic mapping methods in the literature utilize 2.25 times area overheads [5]. We show that this practice is an excessive measure and disregards the features of logic functions and nano-crossbars.…”

“…In Figure 1, a successful mapping process is shown. Different mapping methods such as integer linear programming, satisfiability, graph embedding and bipartite matching are used [5]. In this paper, we choose two approaches: a greedy heuristic method with matrix matching having the smallest runtime [9] and a memetic algorithm using bipartite matching having the highest success rate [10].…”

“…High defect rates of nano-crossbars complicate the logic mapping that generally necessitates area overheads [5]. In this paper, we use the term yield as the percentage of a nanocrossbar utilized to realize a given logic function.…”

Defect-Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation

“…Indeed, this problem is very similar to the logic mapping of reconfigurable nano-crossbar arrays (using AND-OR logic) for which a quite mature literature exists. 7,8 However, most of the mentioned studies focus on a single plane of crossbar, particularly AND, and neglect the OR plane. Furthermore, the related algorithms operate using 1.5 times larger crossbars and show poor performance for optimum-size crossbars.…”

A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays

“…Although defect/fault tolerant logic mapping for nanocrossbars has been long studied [16], research on variation tolerance is relatively new. First, Gojman and Dehon consider variations on crosspoint transistor parameters to accurately determine the placement of defects as opposed to using randomly assigned defect maps [17].…”