Defect-Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation

Tunali, Onur; Morgül, M. Ceylan; Altun, Mustafa

doi:10.1109/mm.2018.053631138

Cited by 6 publications

(16 citation statements)

References 11 publications

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“…Note that, required number of cycles is only 7 for [44]. This number can even be reduced to 5 with the proposed technique [43]. On the other hand, as stated in [45], the method in [44] can support the method MAGIC.…”

Section: Textmentioning

confidence: 93%

“…Given that targeted technologies have different performance characteristics, to perform fair comparison, their dependencies on target function should be analyzed. Previously, we have analyzed and extracted delay and power characteristic with dependencies on given function for memristor crossbars [43]. In this study, we present delay and power model for diode, FET, and fourterminal lattice.…”

Section: Overview Of Circuit Design Steps a Backgroundmentioning

confidence: 99%

“…We have called phase combination-0 and phase combination-1 realization, if realization is happened based on an output itself and its negation, respectively. For instance, for the realization of phase combination-1, first its negation is produced [43] and at last original function outputs. Based on this property, array size of memristive crossbars can be optimized.…”

Section: B Proposed Greedy Algorithm For Two-level Multi Output Synthesis For Memristive Arraysmentioning

confidence: 99%

“…The realization in [44] is phase combination-1 realization. initial Greedy Algorithm (GA-initial) [43] and Proposed Greedy Algorithm (PGA)…”

Section: B Proposed Greedy Algorithm For Two-level Multi Output Synthesis For Memristive Arraysmentioning

confidence: 99%

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Circuit Design Steps for Nano-Crossbar Arrays: Area-Delay-Power Optimization With Fault Tolerance

Morgül

Frontini

Tunali

et al. 2021

IEEE Trans. Nanotechnology

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Nano-crossbar arrays have emerged to achieve high performance computing beyond the limits of current CMOS with the drawback of higher fault rates. They offer area and power efficiency in terms of their easy-to-fabricate and dense physical structures. They consist of regularly placed crosspoints as computing elements, which behave as diode, memristor, field effect transistor, or novel four-terminal switching devices. In this study, we establish a complete design framework for crossbar circuits explaining and analyzing every step of the process. We comparatively elaborate on these technologies in the sense of their capabilities for computation regarding area including a new logic synthesis technique for memristors, fault tolerance including a novel paradigm for four-terminal devices, delay, and power consumption. As a result, this study introduces a synthesis methodology that considers basic technology preference for switching crosspoints and fault rates of the given crossbar as well as their effects on performance metrics including power, delay, and area.

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Section: Textmentioning

confidence: 93%

Section: Overview Of Circuit Design Steps a Backgroundmentioning

confidence: 99%

Section: B Proposed Greedy Algorithm For Two-level Multi Output Synthesis For Memristive Arraysmentioning

confidence: 99%

“…The realization in [44] is phase combination-1 realization. initial Greedy Algorithm (GA-initial) [43] and Proposed Greedy Algorithm (PGA)…”

Section: B Proposed Greedy Algorithm For Two-level Multi Output Synthesis For Memristive Arraysmentioning

confidence: 99%

See 2 more Smart Citations

Circuit Design Steps for Nano-Crossbar Arrays: Area-Delay-Power Optimization With Fault Tolerance

Morgül

Frontini

Tunali

et al. 2021

IEEE Trans. Nanotechnology

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“…On the other hand, with the discovery of the memristor (memory element) and its efficient use in crossbar arrays offering dense and regular structures [9][10][11], it is possible to perform multiplication and addition operations in the analog domain in a very effective way [12][13][14].…”

Section: Introductionmentioning

confidence: 99%

Analog Neural Network based on Memristor Crossbar Arrays

Yildiz

Altun

Gungordu

et al. 2019

2019 11th International Conference on Electrical and Electronics Engineering (ELECO)

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In this paper, a new feed forward analog neural network is designed using a memristor based crossbar array architecture. This structure consists of positive and negative polarity connection matrices. In order to show the performance and usefulness of the proposed circuit, it is considered a sample application of iris data recognition. The proposed neural network implementation is approved by the simulation in Cadence design environment using 0.35µm CMOS technology. The results obtained are promising for the implementation of high density neural network.

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Electrochemical‐Memristor‐Based Artificial Neurons and Synapses—Fundamentals, Applications, and Challenges

et al. 2023

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Artificial neurons and synapses are considered essential for the progress of the future brain‐inspired computing, based on beyond von Neumann architectures. Here, a discussion on the common electrochemical fundamentals of biological and artificial cells is provided, focusing on their similarities with the redox‐based memristive devices. The driving forces behind the functionalities and the ways to control them by an electrochemical‐materials approach are presented. Factors such as the chemical symmetry of the electrodes, doping of the solid electrolyte, concentration gradients, and excess surface energy are discussed as essential to understand, predict, and design artificial neurons and synapses. A variety of two‐ and three‐terminal memristive devices and memristive architectures are presented and their application for solving various problems is shown. The work provides an overview of the current understandings on the complex processes of neural signal generation and transmission in both biological and artificial cells and presents the state‐of‐the‐art applications, including signal transmission between biological and artificial cells. This example is showcasing the possibility for creating bioelectronic interfaces and integrating artificial circuits in biological systems. Prospectives and challenges of the modern technology toward low‐power, high‐information‐density circuits are highlighted.

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Defect-Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation

Cited by 6 publications

References 11 publications

Circuit Design Steps for Nano-Crossbar Arrays: Area-Delay-Power Optimization With Fault Tolerance

Circuit Design Steps for Nano-Crossbar Arrays: Area-Delay-Power Optimization With Fault Tolerance

Analog Neural Network based on Memristor Crossbar Arrays

Electrochemical‐Memristor‐Based Artificial Neurons and Synapses—Fundamentals, Applications, and Challenges

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