2015
DOI: 10.1109/tvlsi.2014.2334642
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A Sub-mW, Ultra-Low-Voltage, Wideband Low-Noise Amplifier Design Technique

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Cited by 113 publications
(53 citation statements)
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“…Reducing the supply voltage of CMOS circuitry has dramatic impacts on the performance of the transistors [6]. For example, the intrinsic voltage gain of the transistors is dramatically reduced at low V DS values, and this is mainly due to an increase in the output conductance of the devices.…”
Section: Introductionmentioning
confidence: 99%
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“…Reducing the supply voltage of CMOS circuitry has dramatic impacts on the performance of the transistors [6]. For example, the intrinsic voltage gain of the transistors is dramatically reduced at low V DS values, and this is mainly due to an increase in the output conductance of the devices.…”
Section: Introductionmentioning
confidence: 99%
“…For example, the intrinsic voltage gain of the transistors is dramatically reduced at low V DS values, and this is mainly due to an increase in the output conductance of the devices. Furthermore, the transit frequency drops and the minimum noise figure increases, mostly due to a reduction in the achievable g m [6]. Additionally, the requirements of ultra-low power (ULP) (P diss < 0.5 mW) design lead to strict restrictions on the design options and the overall speed of the circuits.…”
Section: Introductionmentioning
confidence: 99%
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