A Sub-35 pW Axon-Hillock artificial neuron circuit

Danneville, F.; Loyez, Christophe; Carpentier, Kévin; Sourikopoulos, Ilias; Mercier, Éric; Cappy, A.

doi:10.1016/j.sse.2019.01.002

Cited by 33 publications

(45 citation statements)

References 4 publications

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“…Analysing the low-power A-H implementation proposed in Ref. [5], it has fewer transistors on the circuit, composed by just two inverters (M1-M4) with the same feedback capacitor C fb from regular A-H. Some modifications were applied to the original circuit trying to reduce power consumption drastically and achieve higher energy efficiency for each spike.…”

Section: Low-power Axon-hillockmentioning

confidence: 99%

“…The need for computational systems with high processing capacity and, as always, greater energy efficiency led the studies of neuromorphic circuits to be, replaced or used alongside the von Neumann architecture on conventional processors, where tasks that require neural networks would be processed. The development and implementation of microelectronic circuits with similar functions to biological neurons are presented in many works [5][6][7]. These works propose different approaches used in several practical applications, some more focused on the electrophysiology of neurons and others on the ability to create highly dense neural networks.…”

Section: Introductionmentioning

confidence: 99%

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Low‐power hybrid memristor‐CMOS spiking neuromorphic STDP learning system

Maranhão

Guimarães

2021

IET Circuits, Devices & Syst

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An electronic circuit that implements a neural network architecture with spike neurons was studied, proposed, and evaluated, primarily considering energy consumption. In this way, CMOS transistors were used to implement neurons, memristors were used to work as synapses, and the proposed network has a spike‐timing‐dependent plasticity (STDP) learning aspect. The validation of the circuit modules and the complete network architecture was performed using SPICE models. Since most data of company technologies is restricted, some universities provide predictive models to reproduce the real ones. In this paper, two types of Integrate and Fire Neuron (I&F) using 32 nm CMOS technology simulated in LTspice with BSIM4v4 model designed by Berkley University and applying predictive parameters provided by Predictive Technology Model (PTM) are presented. The simulation results obtained here reduces the bias voltage and the chip size to the most recent designs implemented. Finally, communication between neurons and synapses with STDP learning has been successfully simulated.

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Section: Low-power Axon-hillockmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Low‐power hybrid memristor‐CMOS spiking neuromorphic STDP learning system

Maranhão

Guimarães

2021

IET Circuits, Devices & Syst

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“…In reference [9], for achieving extremely low DC power consumption and energy efficiency, a refined AH architecture was presented (see Figure 2). F I G U R E 1 Mathematical model waveforms and systematic parameter description [5] F I G U R E 2 Refined single ended AH artificial neuron [9] DALIRI ET AL.…”

Section: Ah Neuronmentioning

confidence: 99%

A comparative study between E‐neurons mathematical model and circuit model

Daliri

Ferreira

Klisnick

et al. 2021

IET Circuits, Devices & Syst

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The basic concepts and techniques involved in the development and analysis of mathematical models for individual neurons are reviewed. A spiking neuron model uses differential equations to represent various neuronal activities that have more compatibility with circuit criteria and are chosen for developing a comparative study with circuit models. For this comparison, a new fully differential neuron that uses the fully differential aspects to reach more balanced differential equations to mathematical model is presented. This comparative study of the circuit model and a neuron mathematical model provides a quantitative understanding of the challenges between mathematical models and microelectronic circuit design criteria.

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“…Spiking Neural Networks display promising characteristics for this paradigm change [23], [25], [30], [34], such as unsupervised training with STDP rules, which reduces the need for large annotated datasets. SNNs show higher efficiency than classical neural networks, from both computation [18] and energy [8] points of view. First, regarding computation, with temporal coding (see Section I-C), the core information in SNN models lies in the very timing of binary spikes, and do no require to manipulate large matrices of floating-point numbers.…”

Section: Introductionmentioning

confidence: 99%

A critical survey of STDP in Spiking Neural Networks for Pattern Recognition

Vigneron

Martinet

2020

2020 International Joint Conference on Neural Networks (IJCNN)

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The bio-inspired concept of Spike-Timing-Dependent Plasticity (STDP) derived from neurobiology is increasingly used in Spiking Neural Networks (SNNs) nowadays. Mostly found in unsupervised learning, though recent work has shown its usefulness in supervised or reinforced paradigms too, STDP is a key element to understanding SNN architectures' learning process. This review introduces a categorisation of its several variants and discusses their specificities and applications, from a pattern recognition perspective. It gathers a variety of definitions used in machine learning for pattern recognition. It provides relevant information for research communities of various backgrounds looking for an overview of this field.

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A Sub-35 pW Axon-Hillock artificial neuron circuit

Cited by 33 publications

References 4 publications

Low‐power hybrid memristor‐CMOS spiking neuromorphic STDP learning system

Low‐power hybrid memristor‐CMOS spiking neuromorphic STDP learning system

A comparative study between E‐neurons mathematical model and circuit model

A critical survey of STDP in Spiking Neural Networks for Pattern Recognition

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A Sub-35 pW Axon-Hillock artificial neuron circuit

Cited by 33 publications

References 4 publications

Low‐power hybrid memristor‐CMOS spiking neuromorphic STDP learning system

Low‐power hybrid memristor‐CMOS spiking neuromorphic STDP learning system

A comparative study between E‐neurons mathematical model and circuit model

A critical survey of STDP in Spiking Neural Networks for Pattern Recognition

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Product

Resources

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A Sub-35 pW Axon-Hillock artificial neuron circuit