A Sub-200 fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications

Catli, Burak; Nazemi, Ali; Ali, Tamer; Fallahi, Siavash; Liu, Yang; Kim, Jaehyup; Abdul-Latif, Mohammed; Ahmadi, Mahmood; Maarefi, Hassan; Momtaz, Afshin; Kocaman, Namik

doi:10.1109/cicc.2013.6658471

Cited by 5 publications

(3 citation statements)

References 10 publications

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“…An active capacitance multiplier circuit shown in Fig. 10 is used to create the desired time constant with less actual capacitance area [14], [15]. By using a 20 capacitance multiplication ratio, a 70% reduction in the loop filter area is achieved.…”

Section: Alfmentioning

confidence: 99%

A 2.7 GHz to 7 GHz Fractional-N LC-PLL Utilizing Multi-Metal Layer SoC Technology in 28 nm CMOS

Lee

Kabalican

et al. 2015

IEEE J. Solid-State Circuits

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A fractional-N LC-PLL in 28 nm CMOS that uses vertical layout integration techniques to achieve area reduction without performance penalties is proposed. The design utilizes multi-metal layers to vertically integrate dual interposed inductors on top of the active PLL circuit elements, resulting in an area of 0.07 mm 2 . The PLL covers a wide-frequency range from 2.7 GHz to 7 GHz, consuming a total power of 14 mW. At 7 GHz, the RMS jitter is 0.56 ps in integer mode and 1.1 ps in fractional mode.Index Terms-active loop filter, capacitor multiplier, fractional-N synthesizers, LC-PLL, patterned ground shield, spiral inductor.

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Section: Alfmentioning

confidence: 99%

A 2.7 GHz to 7 GHz Fractional-N LC-PLL Utilizing Multi-Metal Layer SoC Technology in 28 nm CMOS

Lee

Kabalican

et al. 2015

IEEE J. Solid-State Circuits

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“…The phase-locked loop (PLL) based clock generators and frequency multipliers have been widely used in integrated circuit design for microprocessors, digital system-on-chips (SoCs), and wireless communication transceivers [1,2,3,4]. In recent years, multiplying delay-locked loops (MDLLs) [5,6,7,8,9, 10, 11] have been introduced as an alternative to conventional PLLs [1,2,3,4].…”

Section: Introductionmentioning

confidence: 99%

“…In recent years, multiplying delay-locked loops (MDLLs) [5,6,7,8,9, 10, 11] have been introduced as an alternative to conventional PLLs [1,2,3,4]. An MDLL achieves better phase noise performance by periodically injecting a clean reference input clock to the delay line [5,6,7,8].…”

Section: Introductionmentioning

confidence: 99%

A 2–4 GHz fast-locking frequency multiplying delay-locked loop

Kim

Bae

2017

IEICE Electron. Express

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A fast-locking fractional-ratio multiplying DLL (FMDLL) for de-skewed on-chip clock frequency multiplication is presented. A new phase detecting controller (PDC) and a dual-path charge pump (CP) have been adopted to achieve shorter locking time and eliminate lock-in fail problems. The proposed fast-locking FMDLL was implemented in a 65-nm CMOS process and occupies an active area of 0.015 mm 2 . It operates over a frequency range of 2.0-4.0 GHz with a programmable frequency multiplication factor of N/M, where N = 4, 5, 8, 10 and M = 1, 2, 3. It achieves a peak-to-peak output clock jitter of 13.5 ps at 4 GHz while consuming 6.7 mW at 2 GHz from a 1.2 V supply. Compared with the conventional architecture, the locking time has been reduced about 80%.

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A 600 µA 32 kHz Input 960 MHz Output CP-PLL With 530 ps Integrated Jitter in 28 nm FD-SOI Process

Lahiri

Gupta

Kumar

et al. 2015

IEEE J. Solid-State Circuits

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A Sub-200 fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications

Cited by 5 publications

References 10 publications

A 2.7 GHz to 7 GHz Fractional-N LC-PLL Utilizing Multi-Metal Layer SoC Technology in 28 nm CMOS

A 2.7 GHz to 7 GHz Fractional-N LC-PLL Utilizing Multi-Metal Layer SoC Technology in 28 nm CMOS

A 2–4 GHz fast-locking frequency multiplying delay-locked loop

A 600 µA 32 kHz Input 960 MHz Output CP-PLL With 530 ps Integrated Jitter in 28 nm FD-SOI Process

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