A 600 µA 32 kHz Input 960 MHz Output CP-PLL With 530 ps Integrated Jitter in 28 nm FD-SOI Process

Lahiri, Abhirup; Gupta, Nitin; Kumar, Anand; Dhadda, Pradeep

doi:10.1109/jssc.2015.2412680

Cited by 9 publications

(12 citation statements)

References 14 publications

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“…Without changing the PLL loop dynamics or increasing LF capacitor (C INT ), a DP-LF is employed, depicted in its general form in Fig. 2, which reduces the LF resistor noise contribution on output phase noise by a factor of 'M' ('M' = 5 is chosen in our design) with respect to conventional LF ('M = 1') [3]. This is achieved by scaling resistor by factor of 'M', scaling proportional-path capacitor (C PROP ) by '1/M' and splitting each V-I converter unit (in the DAC) into two paths: one part of which scaled by '1/M' is for the proportional path and the other '(M − 1)/M' is for the integral path.…”

Section: Dp-lf For Jitter Reductionmentioning

confidence: 99%

0.012 mm ² 800 µW 0.1–6.4 GHz multi‐protocol PLL with 14 ps _rms integrated jitter in 28 nm FD‐SOI

2016

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A multi-protocol PLL suitable for different wireline standards namely HDMI1.4, USB2.0, DDR4, DisplayPort1.2 and for host clock generation for low-power system-on-chips is presented. The PLL employs automatic VCO gain and charge-pump current calibration circuits to provide a near constant PLL bandwidth which enables a robust jitter performance across process, voltage, temperature. Without increasing the loop-filter capacitor, dual-path loop-filter technique is employed to reduce output jitter due to thermal noise of loop-filter resistor. The PLL designed in 28 nm fully depleted silicon on insulator (FD-SOI) process has an output frequency range from 0.1 to 6.4 GHz, total rms integrated jitter of 14 ps at 21.25 MHz reference frequency, consumes 800 µW at 3.4 GHz VCO frequency and occupies an area of 0.012 mm 2 .

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Section: Dp-lf For Jitter Reductionmentioning

confidence: 99%

0.012 mm ² 800 µW 0.1–6.4 GHz multi‐protocol PLL with 14 ps _rms integrated jitter in 28 nm FD‐SOI

2016

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“…By reducing the current of the charge pump, the loop filter (capacitor) area can be reduced without affecting the bandwidth of the loop. However, the noise and phase errors of the CDR increase by reducing the charge pump current [3]. These issues mentioned above make further development of analogue CDRs in deep submicron processes difficult [4].…”

mentioning

confidence: 99%

8–10 Gbit/s full synthesised continuous‐half‐rate reference‐less all‐digital CDR with sub‐harmonic frequency extraction

Lee

Park

et al. 2018

Electron. lett.

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Continuous-rate all-digital reference-less clock and data recovery (CDR) circuit that utilises a sub-harmonic extraction scheme for wide-range frequency detection is presented. In the proposed CDR, the capture range of the frequency locked loop (FLL) is extended to the tuning range of digital controlled oscillator, thanks to the subharmonic extraction scheme. The frequency errors of FLL in lock state are within the tracking range of CDR loop. The prototype referenceless all-digital CDR, fabricated using a 40 nm CMOS technology, successfully detects 8-10 Gbit/s PRBS 2 31 − 1 data and produces the recovered clock. The CDR consumes 29 mW from a supply voltage of 1 V for 10 Gbit/s input data. The measured RMS jitter of the recovered clock is 2.24 ps.

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“…1 are widely used due to its good current matching, fast switching speed and low power consumption. However, the reverse sub-threshold leakage of this SSCP [3] leads to large the spur level of PLL, especially in the PLL implemented in nanometre CMOS process. As shown in Fig.…”

mentioning

confidence: 99%

“…To compensate the reverse leakage, an auxiliary loop [6] can be used, with much power and area cost. The compensation technique [3] can solve this problem, but the mismatch of up and down current cannot be suppressed.…”

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confidence: 99%

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Source‐switched charge pump with reverse leakage compensation technique for spur reduction of wideband PLL

et al. 2016

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A source-switched charge pump (SSCP) with reverse leakage compensation technique is proposed to reduce spur level of wideband PLL induced by the reverse sub-threshold leakage of the charge pump. This technique can set the source-drain voltage of current-source N-type MOS (NMOS)/P-type MOS to be close to zero at off-state of the charge pump and thus reduce the reverse leakage. Compared with the conventional SSCP, only one NMOS capacitor, two CMOS switches and two inverters are added in the proposed charge pump. So, there is negligible extra power and extra area cost. A 0.7-1.6 GHz PLL is designed with the conventional and the proposed charge pumps in 65 nm CMOS process. Simulation results show the proposed SSCP can reduce orders of the magnitude of the reverse leakage without the penalty of current matching, compared with the conventional charge pump. The PLL with the proposed charge pump achieves up to 28 dB spur level reduction.

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A 600 µA 32 kHz Input 960 MHz Output CP-PLL With 530 ps Integrated Jitter in 28 nm FD-SOI Process

Cited by 9 publications

References 14 publications

0.012 mm ² 800 µW 0.1–6.4 GHz multi‐protocol PLL with 14 ps _rms integrated jitter in 28 nm FD‐SOI

0.012 mm ² 800 µW 0.1–6.4 GHz multi‐protocol PLL with 14 ps _rms integrated jitter in 28 nm FD‐SOI

8–10 Gbit/s full synthesised continuous‐half‐rate reference‐less all‐digital CDR with sub‐harmonic frequency extraction

Source‐switched charge pump with reverse leakage compensation technique for spur reduction of wideband PLL

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A 600 µA 32 kHz Input 960 MHz Output CP-PLL With 530 ps Integrated Jitter in 28 nm FD-SOI Process

Cited by 9 publications

References 14 publications

0.012 mm 2 800 µW 0.1–6.4 GHz multi‐protocol PLL with 14 ps rms integrated jitter in 28 nm FD‐SOI

0.012 mm 2 800 µW 0.1–6.4 GHz multi‐protocol PLL with 14 ps rms integrated jitter in 28 nm FD‐SOI

8–10 Gbit/s full synthesised continuous‐half‐rate reference‐less all‐digital CDR with sub‐harmonic frequency extraction

Source‐switched charge pump with reverse leakage compensation technique for spur reduction of wideband PLL

Contact Info

Product

Resources

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0.012 mm ² 800 µW 0.1–6.4 GHz multi‐protocol PLL with 14 ps _rms integrated jitter in 28 nm FD‐SOI

0.012 mm ² 800 µW 0.1–6.4 GHz multi‐protocol PLL with 14 ps _rms integrated jitter in 28 nm FD‐SOI