A 2–4 GHz fast-locking frequency multiplying delay-locked loop

Kim, Jongsun; Bae, Bongho

doi:10.1587/elex.13.20161056

Cited by 4 publications

(4 citation statements)

References 13 publications

(18 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The voltage-controlled oscillator (VCO) [11][12][13] linearly converts the input control voltage into the output frequency. The circuit structure of the LC voltage-controlled oscillator in this work is shown in the Figure 4.…”

Section: Low-voltage Vcomentioning

confidence: 99%

“…Using the prediction model proposed in this paper to predict the RC network at nodes A and B, and add it to the netlist of the pre-simulation, the influence of the backend parasitic should be predicted in the pre-simulation stage; this would greatly reduce the design cycle. The voltage-controlled oscillator (VCO) [11][12][13] linearly converts the input control voltage into the output frequency. The circuit structure of the LC voltage-controlled oscillator in this work is shown in the Figure 4.…”

Section: Low-voltage Vcomentioning

confidence: 99%

See 1 more Smart Citation

Pre-Layout Parasitic-Aware Design Optimizing for RF Circuits Using Graph Neural Network

Zhang

2023

Electronics

View full text Add to dashboard Cite

The performance of analog and RF circuits is widely affected by the interconnection parasitic in the circuit. With the progress of technology, interconnection parasitics plays a larger role in performance deterioration. To solve this problem, designers must repeat layout design and validation process. In order to achieve an upgrade in the design efficiency, in this paper, a Graph Neural Network (GNN)-based pre-layout parasitic parameter prediction method is proposed and applied to the design optimization of a 28 nm PLL. With the new method adopted, the frequency band overlap rate of the VCO is improved by 2.3 percents for an equal design effort. Similarly, the optimized CP is superior to the traditional method with a 15 ps mismatch time. These improvements are achieved under the premise of greatly saving the optimization iteration and verification costs.

show abstract

Section: Low-voltage Vcomentioning

confidence: 99%

Section: Low-voltage Vcomentioning

confidence: 99%

Pre-Layout Parasitic-Aware Design Optimizing for RF Circuits Using Graph Neural Network

Zhang

2023

Electronics

View full text Add to dashboard Cite

show abstract

“…The fractional-N RF synthesizer is essential to wireless communication systems. It is required to generate a low phase noise and low spur LO while achieving low power consumption [1,2,3,4,5,6,7,8]. Reducing the supply voltage is an effective way to reduce power consumption.…”

Section: Introductionmentioning

confidence: 99%

A 0.7V 1.6mW fractional-N synthesizers for BLE RF transceiver in 40nm CMOS

Chen

2022

IEICE Electron. Express

View full text Add to dashboard Cite

This paper presents a low-power fractional-N synthesizer for BLE with a gate-switching charge pump (CP) and high-speed prescaler. To reduce the current mismatch under low supply voltage, a master-slave rail-to-rail operational trans-conductance amplifier (OTA) structure is employed to the CP; Current self-matching technique guarantees the charging current is equal to discharging current. The embedded logic gates and power switch technique are employed to true-single-phase-clock (TSPC) to reduce power consumption and improve the operating speed of the divider. Random dither is injected into the ∆Σ modulator to prolong the period of output sequence. The proposed phase-locked loop (PLL) is implemented in the 40-nm CMOS process. It achieves −85.94 dBc/Hz@100 kHz and −109.18 dBc/Hz@1 MHz in fractional-N mode while consuming 1.6 mW under a 0.7 V voltage supply.

show abstract

“…Also, PLLs usually have relatively high jitter or phase noise characteristics. Recently, multiplying delay-locked loops (MDLLs) [11][12][13][14][15][16][17][18][19][20][24][25][26][27][28][29][30], a type of injection-locked voltage-controlled oscillators (VCOs), have received considerable attention as on-chip clock generators for digital ICs and highperformance system-on-chips (SoCs) owing to their excellent jitter and stability performance. A typical MDLL can generate an output frequency that is N times the input clock frequency, where N is an integer.…”

Section: Introductionmentioning

confidence: 99%

A low-jitter 2.4 GHz all-digital MDLL with a dithering jitter reduction scheme for 256 times frequency multiplication

Park

Kim

2020

IEICE Electron. Express

Self Cite

View full text Add to dashboard Cite

A new all-digital multiplying delay-locked loop (MDLL) based frequency multiplier architecture with a high frequency multiplication factor N of 256 is presented. The proposed MDLL utilizes a dithering jitter reduction scheme based on a delta-sigma modulation to achieve a low deterministic jitter and a large N factor. Additionally, a new stochastic phase detector is proposed to reduce static phase offset and improve jitter performance. Implemented in a 65-nm 1.0-V CMOS process, the proposed all-digital MDLL generates 2.4-GHz output clock and achieves a peak-to-peak jitter of 6.47 ps with N = 256. It occupies an active area of 0.032 mm 2 and achieves a power efficiency of 0.875 mW/GHz.

show abstract

A 2–4 GHz fast-locking frequency multiplying delay-locked loop

Cited by 4 publications

References 13 publications

Pre-Layout Parasitic-Aware Design Optimizing for RF Circuits Using Graph Neural Network

Pre-Layout Parasitic-Aware Design Optimizing for RF Circuits Using Graph Neural Network

A 0.7V 1.6mW fractional-N synthesizers for BLE RF transceiver in 40nm CMOS

A low-jitter 2.4 GHz all-digital MDLL with a dithering jitter reduction scheme for 256 times frequency multiplication

Contact Info

Product

Resources

About