A Study on the Reliability and Stability of High Voltage 4H-SiC MOSFET Devices

Abstract

Gate oxide reliability measurements of 4H-SiC DMOSFETs were performed using the Time Dependent Dielectric Breakdown (TDDB) technique at 175°C. The oxide lifetime is then plotted as a function of the electric field. The results show the projected oxide lifetime to be > 100 years at an operating field of ~3 MV/cm. Device reliability of 2.0 kV DMOSFETs was studied by stressing the gate with a constant gate voltage of +15 V at a temperature of 175°C, and monitoring the forward I-V characteristics and threshold voltage for device stability. Our very first measurements show very little variation between the pre-stress and post-stress conditions up to 1000 hrs of operation at 175°C. In addition, forward on-current stressing of the MOSFETs show the devices to be stable up to 1000 hrs of operation.

Review and analysis of SiC MOSFETs’ ruggedness and reliability

“…Nevertheless, with the advancement of SiC processing technology, SiC MOSFET gate oxide lifetimes have exhibited gradual improvements in recent years. In 2006, TDDB measurements on 2 kV 4H-SiC DMOSFETs was performed at 175°C and extrapolated the mean time to failure (MTTF) under 3 MV/cm to be longer than 100 years [60]. In 2007, Matocha and Beaupre [61] reported an MTTF of 2300 h at 6 MV/cm and 250°C on MOS capacitors thermally grown with N 2 O and NO annealing.…”

Recent Progress in SiC and GaN Power Devices

“…In 2008, Rutgers University performed TDDB measurement on a SiC MOS structure with NO/NO2 annealing, showing that the mean time to 63% devices failure is 215 hours at 375 °C and under an electric field of 6.4 MV/cm (39) . In 2006, the TDDB test on a 2kV SiC DMOSFET at 175 °C and under an electric field of 3 MV/cm showed that the projected lifetime can reach 100 years under normal operation condition (40) . In 2010, Rutgers University found that the reliability projection model for SiC MOS structure under high electric field condition deviates from that under relatively low electric field condition (3 MV/cm).…”

Tailoring Oxide/Silicon Carbide Interfaces: NO Annealing and Beyond

“…When it comes to positive charge trapping however, the presence of nitrogen proves to be detrimental to device stability [73,74]. This can be of concern even for n-channel transistors to which a negative gate bias can be applied to ensure that it is OFF in its idle state.…”