A study of Thread Level Parallelism on mobile devices

Cao, Gao; Gutierrez, Anthony; Dreslinski, Ronald G.; Mudge, Trevor; Flautner, Krisztián; Blake, Geoffrey

doi:10.1109/ispass.2014.6844468

Cited by 16 publications

(8 citation statements)

References 3 publications

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“…On the other hand, the desktop TLP study by Blake et al [1] showed the TLP of desktop applications remained relatively low, even after 10 years of effort writing parallelized software. Similarly, we have not seen a significant increase in TLP compared work from one year ago [3]. Clearly, parallelizing software is an extremely challenging problem, particularly for desktop/mobile applications.…”

Section: ) Background Applicationsmentioning

confidence: 51%

“…The GPU and mobile coprocessors on chip also reduce CPU load. All these factors, and the history of the slow pace of exploiting parallelism in desktop and mobile software environments [1,3], indicate that having many powerful cores is over-provisioning. Further analysis suggests that current mobile applications can benefit from a system with the flexbility to satisfy high performance and good energy-efficiency for different application phases.…”

Section: Introductionmentioning

confidence: 99%

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A study of mobile device utilization

Cao

Gutierrez

Rajan

et al. 2015

2015 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

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Mobile devices are becoming more powerful and versatile than ever, calling for better embedded processors. Following the trend in desktop CPUs, microprocessor vendors are trying to meet such needs by increasing the number of cores in mobile device SoCs. However, increasing the number does not translate proportionally into performance gain and power reduction. In the past, studies have shown that there exists little parallelism to be exploited by a multi-core processor in desktop platform applications, and many cores sit idle during runtime. In this paper, we investigate whether the same is true for current mobile applications.We analyze the behavior of a broad range of commonly used mobile applications on real devices. We measure their Thread Level Parallelism (TLP), which is the machine utilization over the non-idle runtime. Our results demonstrate that mobile applications are utilizing less than 2 cores on average, even with background applications running concurrently. We observe a diminishing return on TLP with increasing the number of cores, and low TLP even with heavy-load scenarios. These studies suggest that having many powerful cores is over-provisioning. Further analysis of TLP behavior and big-little core energy efficiency suggests that current mobile workloads can benefit from an architecture that has the flexibility to accommodate both high performance and good energy-efficiency for different application phases.

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Section: ) Background Applicationsmentioning

confidence: 51%

Section: Introductionmentioning

confidence: 99%

A study of mobile device utilization

Cao

Gutierrez

Rajan

et al. 2015

2015 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

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“…The communication rate column presents the amount of communication between threads required during the application execution, which involves synchronizations and data exchange. The TLP metric is used to characterize the amount of concurrency exhibited by the program, as defined by the authors in [14]. The closer this value is to the total number of threads, the more TLP is available.…”

Section: A Benchmarksmentioning

confidence: 99%

On the influence of static power consumption in multicore embedded systems

Lorenzon

Márcia

Beck

2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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Energy consumption in multicore embedded systems has become a constant concern. Thread-Level Parallelism exploitation may reduce energy consumption because it saves static power consumption of the processor, since performance is obtained. However, as will be shown in this paper, the influence of the static power on the energy consumption and Energy-Delay Product will depend on how significant it is in the processor. By evaluating different levels of static power in the respect to the total power consumption in two embedded processors (ARM and Atom), we demonstrate that if the right value of static power consumption is tuned during the designing and manufacturing, it is possible to save up 35% in energy consumption and achieve up to 20% of improvements in the EDP efficiency (i.e., the best possible use of the available resources). We also show that the more communication the parallel application has, the lower is the impact of static power of the processor in the total energy consumption.

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“…This primarily includes performance and energy centric optimizations [59,39,4,8,11,17,19,18,1,55], memory centric optimization [38,2,41,34,56,40], IP related optimizations [21,30,36,48,50,31,22,53,27] and platform development for analyzing these systems [28,47,9,32]. However, to the best of our knowledge, this is probably the first effort to bring IP scheduling from software to hardware and combining it with memory bypassing for optimizing energy, performance and QoS in handhelds.…”

Section: Related Workmentioning

confidence: 99%

Vip

Nachiappan

Zhang

Ryoo

et al. 2015

Proceedings of the 42nd Annual International Symposium on Computer Architecture

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Energy-efficient user-interactive and display-oriented applications on handhelds rely heavily on multiple accelerators (termed IP cores) to meet their periodic frame processing needs. Further, these platforms are starting to host multiple applications concurrently on the multiple CPU cores. Unfortunately, today's hardware exposes an interface that forces the host software (Android drivers) to treat each IP core as an isolated device. Consequently, the host CPU has to get involved in the (i) processing of each frame, (ii) scheduling them to ensure timely progress through the IP cores to meet their QoS needs, and (iii) explicitly having to move data from one IP core to the next, with main memory serving as the common staging area.We show in this paper through measurements on a Nexus 7 platform that the frequent invocation of the CPU for processing these frames and the involvement of main memory as a data flow conduit, are serious limitations. Instead, we propose a novel IP virtualization framework (VIP), involving three key ideas that allow several IPs to be chained together and made to appear to the software as a single device. First, chaining of IPs avoids data transfer through the memory system, enhancing the throughput of flows through the IPs. Second, by using a burst-mode, the CPU can initiate the processing of several frames through the virtual IP chain, without getting involved (and interrupted) for each frame, thereby allowing better energy saving and utilization opportunities. Removing the CPU from this loop, requires alternate orchestration of frame flows to ensure QoS guarantees for each frame of each application. Our third enhancement in VIP creates several virtual paths, one for each flow, through these IP chains with Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from Permissions@acm.org. ISCA '15,

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A study of Thread Level Parallelism on mobile devices

Cited by 16 publications

References 3 publications

A study of mobile device utilization

A study of mobile device utilization

On the influence of static power consumption in multicore embedded systems

Vip

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