A Study of NoC Topologies and Switching Arbitration Mechanisms

Chang, Yung-Chang; Chiu, Ching-Te

doi:10.1109/hpcc.2012.241

Cited by 2 publications

(2 citation statements)

References 10 publications

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“…Figure 2 shows the 4x4 and 8x8 mesh topologies. Currently, 2D mesh topology is widely used by researchers due to accepted wire cost and high bandwidth [8]. In a mesh topology, nodes is connected as a grid.…”

Section: Related Workmentioning

confidence: 99%

Performances analysis of reducing router in ring and mesh topology for network-on-chip (NoC) architecture

Phing

Warip

Ehkan

et al. 2019

IJEECS

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<span>The size of the transistor has reached physical processor limitation in particular for traditional bus-based and point-to-point architecture in system-on-chip (SoC). Therefore, network-on-chip (NoC) was proposed as a solution. The performances required for the optimization of the NoC are low network latency, low power consumption, small area, and high throughput. However, recently the size of the NoC architecture has increased and the communication between cores to core become complicated. To overcome this disadvantages, topology plays an important role. In this paper, we reduce the number of the router in the 16 cores and 64 cores ring and mesh topologies by connected more numbers of node in each router. Result shows that reducing the number of the router in 64 cores ring topology outperforms the conventional topologies in term of area, power consumption, latency, and accepted packet rate. Reducing router in 64 cores ring topology decrease the average area, power consumption, latency, and increase the average accepted packet rate by 160.45%, 23.88%, 54.76%, and 223.88% over the 64 cores mesh, reducing router in mesh, ring, and cross-link mesh topologies.</span>

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Section: Related Workmentioning

confidence: 99%

Performances analysis of reducing router in ring and mesh topology for network-on-chip (NoC) architecture

Phing

Warip

Ehkan

et al. 2019

IJEECS

View full text Add to dashboard Cite

show abstract

“…The iSLIP is popular due to higher throughput and fairness in routers for NoC based on round-robin strategy [6]. Therefore, lots of researchers have paid more attention to round-robin method combined with NoC tightly.…”

Section: Introductionmentioning

confidence: 99%

BARR: Congestion aware scheduling algorithm for Network-on-Chip router

Wang

et al. 2017

IEICE Electron. Express

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Scheduling algorithm is crucial to the performance of the Network-on-chip router. Different from traditional scheduling algorithms that concentrate on local fairness, we propose a congestion-aware scheduling algorithm based on input buffer of downstream router. The scheduling algorithm keeps a match dynamically between input and output by detecting the flits number to be transferred in the same packet. It can reduce network congestion especially under heavy traffic loads. Compared to RRM and iSLIP algorithm, the new scheduling algorithm can increase the saturation throughput by 8.2% and reduce the average communication latency by 7.8% under non-uniform traffic.

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A Study of NoC Topologies and Switching Arbitration Mechanisms

Cited by 2 publications

References 10 publications

Performances analysis of reducing router in ring and mesh topology for network-on-chip (NoC) architecture

Performances analysis of reducing router in ring and mesh topology for network-on-chip (NoC) architecture

BARR: Congestion aware scheduling algorithm for Network-on-Chip router

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