A Study of Gettering Effect of Metallic Impurities in Silicon

Nakamura, M.; Kato, Toyofumi; Oi, Noboru

doi:10.1143/jjap.7.512

Cited by 42 publications

(12 citation statements)

References 13 publications

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“…In other words, the Ga layer on the surface of the silicon wafer does not play a significant role in Ga gettering but the Ga metal source itself plays an important role in the gettering. These features of' Ga getterir~g are in striking contrast to phosphorus and boron diffusion gettering (5)(6)(7)(8)(9) in which the liquidus glass or high concentration diffused layers on silicon surfaces are important agents.…”

Section: Minority Carrier Liietimes Of Ga-dif]used Wafers--mentioning

confidence: 98%

Gettering of Gold and Copper in Silicon during Gallium Diffusion

Momma

Taniguchi

Ura

et al. 1978

J. Electrochem. Soc.

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The gettering of Au and Cu during the sealed tube diffusion of Ga has been studied by using neutron activation analysis and the spreading resistance microprobe technique. It was found that Au in silicon was gettered during Ga diffusion regardless of the cooling conditions. Most of the Cu in the surface layer of silicon diffused out during Ga diffusion, while Cu in the bulk silicon was gettered during the slow cooling process after diffusion. Increases in the minority carrier lifetime in p+n diodes prepared by Ga diffusion occurred with increasing the amount of Ga used as a source. It was ascertained that in Ga gettering the Ga metal sources played an important role as impurity ~inks.In silicon device processing, high temperature steps, such as oxidation and dopant diffusion, often result in the soft reverse characteristics of pn junctions. The origin of this high leakage current is believed to be the localized high electric field caused by the precipitates of metals, such as Au and Cu (1). These metals in silicon also lead to the degradation of minority carrier lifetime (2-4) which affects the forward voltage drop and other device parameters. These undesired metallic impurities can be removed by so called "gettering" processes. Up to now, various gettering techniques have been reported (5-14). Among them, gettering during diffusion of dopant impurities, such as phosphorus, boron, gallium, and so forth, is most important, because the dopant diffusion is the typical method for making pn junctions. The gettering by phosphorus and boron diffusion has been widely studied analytically and electrically (5-9), but only a few works have been reported concerning the gettering during Ga diffusion (14). Because of the relatively high diffusion coefficient of Ga in silicon, Ga diffusion is often used for the formation of p-type layers of silicon power devices. In these devices high lifetime values are often desirable. Therefore, the maintenance of a minimum lifetime during Ga diffusion is an outstanding problem in the power device processing. Lambert and KShl (14) reported that metallic Ga layers painted on the silicon surface show pronounced gettering effect. However, the precise features of Ga gettering have not been offered yet. It is the purpose of this study to investigate analytically the behavior of Au and Cu in the sealed tube diffusion of Ga and to reveal the mechanism of the gettering during Ga diffusion. ExperimentalSample preparation.--The starting materials used in this study were float-zone, n-type silicon wafers, 130-180 ~-cm, with mechanically lapped surface. The wafers were intentionally contaminated with a moderate to a large amount of Au or Cu to obtain impurity levels above the background level. Au-contaminated samples were prepared by the following procedure. First, the wafers were etched by HF/HNO~ solutions to remove the surface-damaged layer produced by mechanical lapping. Au films were deposited on one side of the silicon wafers by vacuum evaporation and then annealed at 90O~ for 30 rain in an argon a...

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Section: Minority Carrier Liietimes Of Ga-dif]used Wafers--mentioning

confidence: 98%

Gettering of Gold and Copper in Silicon during Gallium Diffusion

Momma

Taniguchi

Ura

et al. 1978

J. Electrochem. Soc.

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“…It has also been shown that the internally gettered iron is often not the precipitate phase. 11 Redissolution of the FeSi 2 phase or release of gettered atomic iron 11 remains hazardous to the surface device area.…”

Section: Introductionmentioning

confidence: 99%

Iron precipitation in float zone grown silicon

Henley

Ramappa

1997

Journal of Applied Physics

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Temperature dependent iron precipitation in float zone grown silicon wafers has been experimentally investigated. Results of iron precipitation experiments over a wide thermal process temperature range and time are presented. Precipitation of iron in silicon was analyzed by a quantitative assessment of change in interstitial iron using a surface photovoltage minority carrier lifetime analysis technique. Contamination levels of iron in the range 10 11 -10 13 atoms/cm 3 are investigated. It is concluded that maximum iron precipitation occurs in the temperature range of 500-600°C. Iron precipitation is rapid in this region where more than 90% of the interstitial iron precipitates in a period of 30 min.

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“…No. 4 and their role as generation-recombination centres [24]. Finally, since emitter phosphorus diffusion processing conditions for transistor No.…”

Section: Common-emitter Current Gainmentioning

confidence: 98%

Dependence of dislocations on emitter phosphorus diffusion conditions and their effects on electrical characteristics of silicon planar NPN transistors

Popović¹,

Stojadinović

1979

Phys. Stat. Sol. (a)

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It is shown that emitter edge dislocations (EED) need not be “distinct from and in addition to diffusion‐induced dislocations (DID)” as generally accepted. Namely, under certain emitter diffusion conditions, when DID just began to appear, EED and DID can become the same dislocations, originally created inside diffused emitter areas, and then, during emitter oxidation step, displaced towards edges of these areas. Also, it is shown that conventional method for EED elimination, although it considerably reduces a low‐frequency noise of planar NPN transistors, has undesirable effects on the other electrical characteristics: increases reverse emitter‐base current at voltages below avalanche breakdown, i.e. causes “soft” breakdown and reduces commonemitter current gain at low current level.

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A Study of Gettering Effect of Metallic Impurities in Silicon

Cited by 42 publications

References 13 publications

Gettering of Gold and Copper in Silicon during Gallium Diffusion

Gettering of Gold and Copper in Silicon during Gallium Diffusion

Iron precipitation in float zone grown silicon

Dependence of dislocations on emitter phosphorus diffusion conditions and their effects on electrical characteristics of silicon planar NPN transistors

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